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* [opcodes] reordered RVC instructionsGravatar Andrew Waterman2011-05-06
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* [xcc,sim,opcodes] added c.addiwGravatar Andrew Waterman2011-04-24
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* [xcc,sim,opcodes] added more RVC instructionsGravatar Andrew Waterman2011-04-24
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* [xcc,sim,opcodes] added rvc conditional branchesGravatar Andrew Waterman2011-04-18
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* [xcc,pk,sim] added privileged cflush instructionGravatar Andrew Waterman2011-04-12
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* [xcc,sim] rvc loads and storesGravatar Andrew Waterman2011-04-12
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* [xcc,sim,opcodes] more rvc instructions and bug fixesGravatar Andrew Waterman2011-04-11
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* [xcc, sim] added rvc insn c.li; misc fixesGravatar Andrew Waterman2011-04-09
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* [xcc,pk,sim,opcodes] added first RVC instructionGravatar Andrew Waterman2011-04-09
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* [pk,sim] fixed parse-opcodes bugGravatar Andrew Waterman2011-04-07
| | | | was causing spurious illegal instruction traps
* [opcodes,pk,sim,xcc] fix utidx - add rdGravatar Yunsup Lee2011-04-06
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* [opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem ↵Gravatar Yunsup Lee2011-04-05
| | | | instructions
* [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Gravatar Yunsup Lee2011-04-04
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* [opcodes,pk,sim,xcc] add vector mem instructionsGravatar Yunsup Lee2011-04-04
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* [opcodes,pk,sim,xcc] add stop,utidx instructionsGravatar Yunsup Lee2011-04-04
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* [opcodes,pk,sim,xcc] add fence instructions for vector unitGravatar Yunsup Lee2011-04-04
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* [opcodes] fixed up instruction tableGravatar Andrew Waterman2011-03-25
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* [opcodes] minor opcode changesGravatar Andrew Waterman2011-03-25
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* [sim,pk,xcc,opcodes] removed fminmag/fmaxmagGravatar Andrew Waterman2011-03-25
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* [xcc,pk,opcodes,sim] updated encoding/insn namesGravatar Andrew Waterman2011-03-25
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* [xcc,opcodes,pk,sim] krste's re-renaming spreeGravatar Andrew Waterman2011-02-15
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* [xcc,sim,opcodes] removed mtflh/mffl/mffhGravatar Andrew Waterman2011-02-15
| | | | in rv32 these will be replaced with loads and stores.
* [sim,xcc,opcodes] added back mtflh.dGravatar Andrew Waterman2011-02-02
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* [opcodes,pk,sim,xcc] synci now bombs whole icacheGravatar Andrew Waterman2011-02-02
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* [xcc,opcodes,pk,sim] cleanup to FP ISAGravatar Andrew Waterman2011-02-01
| | | | | | | - Added 5th rounding mode - Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...) - merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode - made MFFL.D and MFFH.D illegal in RV64
* [opcodes] fixed verilog generation for shiftsGravatar Andrew Waterman2011-01-31
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* [sim,opcodes] add mulhsu instructionGravatar Andrew Waterman2011-01-25
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* [opcodes,pk,sim,xcc] great renumbering of 2011, part deuxGravatar Andrew Waterman2011-01-25
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* [sim, pk, xcc, opcodes] great instruction renaming of 2011Gravatar Andrew Waterman2011-01-20
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* [opcodes, sim, xcc] made *w insns illegal in RV32Gravatar Andrew Waterman2011-01-18
| | | | now generic variants behave differently in RV32 and RV64.
* [opcodes, pk, sim, xcc] removed nor, normalized macros to addiGravatar Andrew Waterman2011-01-17
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* [opcodes,pk,sim,xcc] flip fields to favor little endianGravatar Yunsup Lee2011-01-03
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* [opcodes, pk, sim, xcc] Tweaked FP encodingGravatar Andrew Waterman2010-11-21
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* [opcodes] generate latex and verilog correctlyGravatar Andrew Waterman2010-11-21
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* [xcc, sim, pk, opcodes] new instruction encoding!Gravatar Andrew Waterman2010-11-21
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* [opcodes, pk, sim, xcc] made jumps shorter and PC-relativeGravatar Andrew Waterman2010-11-21
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* [opcodes] add latex table for rm stuffGravatar Yunsup Lee2010-10-31
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* [opcodes] remove .swp fileGravatar Yunsup Lee2010-10-26
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* [sim,xcc,pk,opcodes] static rounding modes for FP insnsGravatar Andrew Waterman2010-10-25
| | | | | | Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
* [opcodes] changed formatting of optab section headersGravatar Andrew Waterman2010-10-20
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* [pk, sim] added FPU emulation support to proxy kernelGravatar Andrew Waterman2010-10-15
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* [xcc] modified opcodes for better FP decode mappingGravatar Andrew Waterman2010-10-07
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* [opcodes] added code field back to syscall/breakGravatar Andrew Waterman2010-10-05
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* [opcodes] updated parse-opcodes for latex tablesGravatar Yunsup Lee2010-10-05
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* [opcodes] update parse-opcodesGravatar Yunsup Lee2010-10-05
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* [xcc, sim] mff now uses rs2 for dataGravatar Andrew Waterman2010-10-02
| | | | this is symmetric with fp stores, so we only need one decoding pipe
* [opcodes, sim, xcc] added mffl.d instructionGravatar Andrew Waterman2010-09-28
| | | | ...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
* [xcc, sim] changed instruction format so imm12 subs for rs2Gravatar Andrew Waterman2010-09-20
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* [xcc, sim] replaced ble/bleu with bge/bgeuGravatar Andrew Waterman2010-09-13
| | | | This will simplify control logic (since every branch has a logical inverse)
* [opcodes] fixed tex table for ish,ishw typesGravatar Yunsup Lee2010-09-12
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