diff options
| author |  Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-18 17:51:52 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-18 17:51:52 -0800 |
| commit | b5770afc54cb5c445db574225d911ce330f62125 (patch) | |
| tree | 012245ab62ee845df840faaf2ff79affdab8ced4 | |
| parent | a6c850798cce0d0107d1da7eac80974aff9bee9e (diff) | |
[opcodes, sim, xcc] made *w insns illegal in RV32
now generic variants behave differently in RV32 and RV64.
| -rw-r--r-- | inst.v | 2 | ||||
| -rw-r--r-- | instr-table.tex | 18 | ||||
| -rw-r--r-- | opcodes | 2 |
3 files changed, 0 insertions, 22 deletions
@@ -47,8 +47,6 @@ `define SRLW 32'b?????_?????_?????_0000010111_1110111 `define SRAW 32'b?????_?????_?????_0000011111_1110111 `define MULW 32'b?????_?????_?????_0000000001_1110111 -`define MULHW 32'b?????_?????_?????_0000010001_1110111 -`define MULHUW 32'b?????_?????_?????_0000011001_1110111 `define DIVW 32'b?????_?????_?????_0000100001_1110111 `define DIVUW 32'b?????_?????_?????_0000101001_1110111 `define REMW 32'b?????_?????_?????_0000110001_1110111 diff --git a/instr-table.tex b/instr-table.tex index ec62ec0..0bbcf13 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -523,24 +523,6 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & MULHW rd,rs1,rs2 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & MULHUW rd,rs1,rs2 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & DIVW rd,rs1,rs2 \\ \cline{2-10} @@ -65,8 +65,6 @@ srlw rd rs1 rs2 16=0 15..10=2 9..7=7 6..0=0x77 sraw rd rs1 rs2 16=0 15..10=3 9..7=7 6..0=0x77 mulw rd rs1 rs2 16..10=0 9..7=1 6..0=0x77 -mulhw rd rs1 rs2 16..10=2 9..7=1 6..0=0x77 -mulhuw rd rs1 rs2 16..10=3 9..7=1 6..0=0x77 divw rd rs1 rs2 16..10=4 9..7=1 6..0=0x77 divuw rd rs1 rs2 16..10=5 9..7=1 6..0=0x77 remw rd rs1 rs2 16..10=6 9..7=1 6..0=0x77 |