diff options
| author |  Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-05 00:50:52 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-05 00:50:52 -0700 |
| commit | 2505985a2162b33478fb7da030575cf7beb953f2 (patch) | |
| tree | 688c415de2990b507689377a1ff1efcabdfb5426 | |
| parent | 57d01f8e913c0fbd07ec61dae082da0db526d5da (diff) | |
[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem instructions
| -rw-r--r-- | inst.v | 102 | ||||
| -rw-r--r-- | opcodes | 156 | ||||
| -rwxr-xr-x | parse-opcodes | 33 |
3 files changed, 199 insertions, 92 deletions
@@ -157,38 +157,74 @@ `define FMSUB_D 32'b?????_?????_?????_?????_???_01_1000111 `define FNMSUB_D 32'b?????_?????_?????_?????_???_01_1001011 `define FNMADD_D 32'b?????_?????_?????_?????_???_01_1001111 -`define LD_V 32'b?????_?????_00000_00000_000_11_0001011 -`define LW_V 32'b?????_?????_00000_00000_000_10_0001011 -`define LWU_V 32'b?????_?????_00000_00000_001_10_0001011 -`define LH_V 32'b?????_?????_00000_00000_000_01_0001011 -`define LHU_V 32'b?????_?????_00000_00000_001_01_0001011 -`define LB_V 32'b?????_?????_00000_00000_000_00_0001011 -`define LBU_V 32'b?????_?????_00000_00000_001_00_0001011 -`define SD_V 32'b00000_?????_00000_?????_010_11_0001011 -`define SW_V 32'b00000_?????_00000_?????_010_10_0001011 -`define SH_V 32'b00000_?????_00000_?????_010_01_0001011 -`define SB_V 32'b00000_?????_00000_?????_010_00_0001011 -`define FLD_V 32'b?????_?????_00000_00000_000_11_0001111 -`define FLW_V 32'b?????_?????_00000_00000_000_10_0001111 -`define FSD_V 32'b00000_?????_00000_?????_010_11_0001111 -`define FSW_V 32'b00000_?????_00000_?????_010_10_0001111 -`define LDST_V 32'b?????_?????_?????_00000_100_11_0001011 -`define LWST_V 32'b?????_?????_?????_00000_100_10_0001011 -`define LWUST_V 32'b?????_?????_?????_00000_101_10_0001011 -`define LHST_V 32'b?????_?????_?????_00000_100_01_0001011 -`define LHUST_V 32'b?????_?????_?????_00000_101_01_0001011 -`define LBST_V 32'b?????_?????_?????_00000_100_00_0001011 -`define LBUST_V 32'b?????_?????_?????_00000_101_00_0001011 -`define SDST_V 32'b00000_?????_?????_?????_110_11_0001011 -`define SWST_V 32'b00000_?????_?????_?????_110_10_0001011 -`define SHST_V 32'b00000_?????_?????_?????_110_01_0001011 -`define SBST_V 32'b00000_?????_?????_?????_110_00_0001011 -`define FLDST_V 32'b?????_?????_?????_00000_100_11_0001111 -`define FLWST_V 32'b?????_?????_?????_00000_100_10_0001111 -`define FSDST_V 32'b00000_?????_?????_?????_110_11_0001111 -`define FSWST_V 32'b00000_?????_?????_?????_110_10_0001111 +`define LD_V 32'b?????_?????_00000_0000000011_0001011 +`define LW_V 32'b?????_?????_00000_0000000010_0001011 +`define LWU_V 32'b?????_?????_00000_0000000110_0001011 +`define LH_V 32'b?????_?????_00000_0000000001_0001011 +`define LHU_V 32'b?????_?????_00000_0000000101_0001011 +`define LB_V 32'b?????_?????_00000_0000000000_0001011 +`define LBU_V 32'b?????_?????_00000_0000000100_0001011 +`define SD_V 32'b?????_?????_00000_0000010011_0001011 +`define SW_V 32'b?????_?????_00000_0000010010_0001011 +`define SH_V 32'b?????_?????_00000_0000010001_0001011 +`define SB_V 32'b?????_?????_00000_0000010000_0001011 +`define FLD_V 32'b?????_?????_00000_0000001011_0001011 +`define FLW_V 32'b?????_?????_00000_0000001010_0001011 +`define FSD_V 32'b?????_?????_00000_0000011011_0001011 +`define FSW_V 32'b?????_?????_00000_0000011010_0001011 +`define LDST_V 32'b?????_?????_?????_0000100011_0001011 +`define LWST_V 32'b?????_?????_?????_0000100010_0001011 +`define LWUST_V 32'b?????_?????_?????_0000100110_0001011 +`define LHST_V 32'b?????_?????_?????_0000100001_0001011 +`define LHUST_V 32'b?????_?????_?????_0000100101_0001011 +`define LBST_V 32'b?????_?????_?????_0000100000_0001011 +`define LBUST_V 32'b?????_?????_?????_0000100100_0001011 +`define SDST_V 32'b?????_?????_?????_0000110011_0001011 +`define SWST_V 32'b?????_?????_?????_0000110010_0001011 +`define SHST_V 32'b?????_?????_?????_0000110001_0001011 +`define SBST_V 32'b?????_?????_?????_0000110000_0001011 +`define FLDST_V 32'b?????_?????_?????_0000101011_0001011 +`define FLWST_V 32'b?????_?????_?????_0000101010_0001011 +`define FSDST_V 32'b?????_?????_?????_0000111011_0001011 +`define FSWST_V 32'b?????_?????_?????_0000111010_0001011 +`define LDSEG_V 32'b?????_?????_?????_0001000011_0001011 +`define LWSEG_V 32'b?????_?????_?????_0001000010_0001011 +`define LWUSEG_V 32'b?????_?????_?????_0001000110_0001011 +`define LHSEG_V 32'b?????_?????_?????_0001000001_0001011 +`define LHUSEG_V 32'b?????_?????_?????_0001000101_0001011 +`define LBSEG_V 32'b?????_?????_?????_0001000000_0001011 +`define LBUSEG_V 32'b?????_?????_?????_0001000100_0001011 +`define SDSEG_V 32'b?????_?????_?????_0001010011_0001011 +`define SWSEG_V 32'b?????_?????_?????_0001010010_0001011 +`define SHSEG_V 32'b?????_?????_?????_0001010001_0001011 +`define SBSEG_V 32'b?????_?????_?????_0001010000_0001011 +`define FLDSEG_V 32'b?????_?????_?????_0001001011_0001011 +`define FLWSEG_V 32'b?????_?????_?????_0001001010_0001011 +`define FSDSEG_V 32'b?????_?????_?????_0001011011_0001011 +`define FSWSEG_V 32'b?????_?????_?????_0001011010_0001011 +`define LDSEGST_V 32'b?????_?????_?????_?????_000_11_0001111 +`define LWSEGST_V 32'b?????_?????_?????_?????_000_10_0001111 +`define LWUSEGST_V 32'b?????_?????_?????_?????_001_10_0001111 +`define LHSEGST_V 32'b?????_?????_?????_?????_000_01_0001111 +`define LHUSEGST_V 32'b?????_?????_?????_?????_001_01_0001111 +`define LBSEGST_V 32'b?????_?????_?????_?????_000_00_0001111 +`define LBUSEGST_V 32'b?????_?????_?????_?????_001_00_0001111 +`define SDSEGST_V 32'b?????_?????_?????_?????_100_11_0001111 +`define SWSEGST_V 32'b?????_?????_?????_?????_100_10_0001111 +`define SHSEGST_V 32'b?????_?????_?????_?????_100_01_0001111 +`define SBSEGST_V 32'b?????_?????_?????_?????_100_00_0001111 +`define FLDSEGST_V 32'b?????_?????_?????_?????_010_11_0001111 +`define FLWSEGST_V 32'b?????_?????_?????_?????_010_10_0001111 +`define FSDSEGST_V 32'b?????_?????_?????_?????_110_11_0001111 +`define FSWSEGST_V 32'b?????_?????_?????_?????_110_10_0001111 +`define MOV_VV 32'b?????_?????_00000_1000000000_0001011 +`define MOV_SV 32'b?????_?????_00000_1000000001_0001011 +`define MOV_SU 32'b?????_?????_?????_1000000010_0001011 +`define MOV_US 32'b?????_?????_?????_1000000011_0001011 +`define FMOV_VV 32'b?????_?????_00000_1100000000_0001011 +`define FMOV_SV 32'b?????_?????_00000_1100000001_0001011 +`define FMOV_SU 32'b?????_?????_?????_1100000010_0001011 +`define FMOV_US 32'b?????_?????_?????_1100000011_0001011 `define VCFGIVL 32'b?????_?????_????????????_000_1110011 `define SETVL 32'b?????_?????_000000000000_001_1110011 -`define VF 32'b00000_00000_????????????_010_1110011 -`define MOV_VV 32'b?????_?????_000000000000_011_1110011 -`define FMOV_VV 32'b?????_?????_000000000000_100_1110011 +`define VF 32'b00000_?????_????????????_010_1110011 @@ -108,6 +108,8 @@ amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3 fence.i rd rs1 imm12 9..7=1 6..2=0x0B 1..0=3 fence rd rs1 imm12 9..7=2 6..2=0x0B 1..0=3 + +# vector fence instructions fence.l.v rd rs1 imm12 9..7=4 6..2=0x0B 1..0=3 fence.g.v rd rs1 imm12 9..7=5 6..2=0x0B 1..0=3 fence.l.cv rd rs1 imm12 9..7=6 6..2=0x0B 1..0=3 @@ -115,6 +117,8 @@ fence.g.cv rd rs1 imm12 9..7=7 6..2=0x0B 1..0=3 syscall 31..27=0 26..22=0 21..17=0 16..7=0 6..2=0x1D 1..0=3 break 31..27=0 26..22=0 21..17=0 16..7=1 6..2=0x1D 1..0=3 + +# vector scalar instructions stop 31..27=0 26..22=0 21..17=0 16..7=2 6..2=0x1D 1..0=3 utidx 31..27=0 26..22=0 21..17=0 16..7=3 6..2=0x1D 1..0=3 @@ -204,46 +208,112 @@ fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 -ld.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lw.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lh.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lb.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 - -sd.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -sw.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -sh.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=1 6..2=0x02 1..0=3 -sb.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=0 6..2=0x02 1..0=3 - -fld.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -flw.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 - -fsd.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -fsw.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -ldst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lwst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lhst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lbst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3 - -sdst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -swst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -shst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=1 6..2=0x02 1..0=3 -sbst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=0 6..2=0x02 1..0=3 - -fldst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -flwst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 - -fsdst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -fswst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -vcfgivl rd rs1 imm12 9..7=0 6..2=0x1C 1..0=3 -setvl rd rs1 21..10=0 9..7=1 6..2=0x1C 1..0=3 -vf 31..27=0 26..22=0 imm12 9..7=2 6..2=0x1C 1..0=3 -mov.vv rd rs1 21..10=0 9..7=3 6..2=0x1C 1..0=3 -fmov.vv rd rs1 21..10=0 9..7=4 6..2=0x1C 1..0=3 +# vector mem instructions + +# 3=d +# 2=seg 2=w +# 1=st 1=st 1=f 1=s 1=h +# 0=u 0=ld 0=x 0=u 0=b +# ---------------------------------------------------------------------------- +# mem padding type ldst x/f u/s width opcode +# unit stride | | | | | | | | +# xloads | | | | | | | | +ld.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +lw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +lwu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +lh.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +lhu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +lb.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +lbu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 +# xstores +sd.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +sw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +sh.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +sb.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +# floads +fld.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +flw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +# fstores +fsd.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +fsw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 + +# mem padding type ldst x/f u/s width opcode +# stride | | | | | | | | +# xloads | | | | | | | | +ldst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +lwst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +lwust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +lhst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +lhust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +lbst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +lbust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 +# xstores +sdst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +swst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +shst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +sbst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +# floads +fldst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +flwst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +# fstores +fsdst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +fswst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 + +# mem padding type ldst x/f u/s width opcode +# segment | | | | | | | | +# xloads | | | | | | | | +ldseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +lwseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +lwuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +lhseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +lhuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +lbseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +lbuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 +# xstores +sdseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +swseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +shseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +sbseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +# floads +fldseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +flwseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +# fstores +fsdseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +fswseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 + +# ldst x/f u/s width opcode +# stride segment | | | | | +# xloads | | | | | +ldsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +lwsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +lwusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=2 6..2=0x03 1..0=3 +lhsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +lhusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=1 6..2=0x03 1..0=3 +lbsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +lbusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=0 6..2=0x03 1..0=3 +# xstores +sdsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +swsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +shsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +sbsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +# floads +fldsegst.v rd rs1 rs2 rs3 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +flwsegst.v rd rs1 rs2 rs3 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 +# fstores +fsdsegst.v rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +fswsegst.v rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# vector arithmetic instructions +mov.vv rd rs1 21..17=0 16=1 15=0 14..12=0 11..7=0 6..2=0x02 1..0=3 +mov.sv rd rs1 21..17=0 16=1 15=0 14..12=0 11..7=1 6..2=0x02 1..0=3 +mov.su rd rs1 rs2 16=1 15=0 14..12=0 11..7=2 6..2=0x02 1..0=3 +mov.us rd rs1 rs2 16=1 15=0 14..12=0 11..7=3 6..2=0x02 1..0=3 +fmov.vv rd rs1 21..17=0 16=1 15=1 14..12=0 11..7=0 6..2=0x02 1..0=3 +fmov.sv rd rs1 21..17=0 16=1 15=1 14..12=0 11..7=1 6..2=0x02 1..0=3 +fmov.su rd rs1 rs2 16=1 15=1 14..12=0 11..7=2 6..2=0x02 1..0=3 +fmov.us rd rs1 rs2 16=1 15=1 14..12=0 11..7=3 6..2=0x02 1..0=3 + +# vector immediate instructions +vcfgivl rd rs1 imm12 9..7=0 6..2=0x1C 1..0=3 +setvl rd rs1 21..10=0 9..7=1 6..2=0x1C 1..0=3 +vf 31..27=0 rs1 imm12 9..7=2 6..2=0x1C 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index 270663e..7ba1bbe 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -26,31 +26,32 @@ arglut['shamtw'] = (14,10) typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,10=b typelut[0x00] = 0 -typelut[0x67] = 1 -typelut[0x6F] = 1 -typelut[0x6B] = 3 -typelut[0x63] = 10 -typelut[0x37] = 2 +typelut[0x03] = 3 +typelut[0x07] = 3 typelut[0x13] = 3 -typelut[0x33] = 4 typelut[0x1B] = 3 -typelut[0x3B] = 4 -typelut[0x03] = 3 typelut[0x23] = 10 -typelut[0x27] = 4 -typelut[0x2F] = 4 -typelut[0x77] = 4 -typelut[0x07] = 3 -typelut[0x0B] = 5 -typelut[0x0f] = 5 typelut[0x27] = 10 -typelut[0x53] = 9 +typelut[0x2B] = 4 +typelut[0x2F] = 4 +typelut[0x33] = 4 +typelut[0x37] = 2 +typelut[0x3B] = 4 typelut[0x43] = 8 typelut[0x47] = 8 typelut[0x4B] = 8 typelut[0x4F] = 8 +typelut[0x53] = 9 +typelut[0x63] = 10 +typelut[0x67] = 1 +typelut[0x6B] = 3 +typelut[0x6F] = 1 +typelut[0x77] = 4 typelut[0x7B] = 4 -typelut[0x2B] = 4 + +# vector opcodes +typelut[0x0B] = 4 +typelut[0x0F] = 5 typelut[0x73] = 3 opcode_base = 0 |