diff options
| author |  Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-04 01:50:56 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-04 02:10:14 -0700 |
| commit | 57d01f8e913c0fbd07ec61dae082da0db526d5da (patch) | |
| tree | a96243fc5b8fdd11893b1e87bbcc3a6bd292d21f | |
| parent | dd6b8266f1d06a0e5acbbed4e8a5fcd3fcd2fcd1 (diff) | |
[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)
| -rw-r--r-- | inst.v | 5 | ||||
| -rw-r--r-- | opcodes | 6 | ||||
| -rwxr-xr-x | parse-opcodes | 1 |
3 files changed, 12 insertions, 0 deletions
@@ -187,3 +187,8 @@ `define FLWST_V 32'b?????_?????_?????_00000_100_10_0001111 `define FSDST_V 32'b00000_?????_?????_?????_110_11_0001111 `define FSWST_V 32'b00000_?????_?????_?????_110_10_0001111 +`define VCFGIVL 32'b?????_?????_????????????_000_1110011 +`define SETVL 32'b?????_?????_000000000000_001_1110011 +`define VF 32'b00000_00000_????????????_010_1110011 +`define MOV_VV 32'b?????_?????_000000000000_011_1110011 +`define FMOV_VV 32'b?????_?????_000000000000_100_1110011 @@ -241,3 +241,9 @@ flwst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 fsdst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 fswst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +vcfgivl rd rs1 imm12 9..7=0 6..2=0x1C 1..0=3 +setvl rd rs1 21..10=0 9..7=1 6..2=0x1C 1..0=3 +vf 31..27=0 26..22=0 imm12 9..7=2 6..2=0x1C 1..0=3 +mov.vv rd rs1 21..10=0 9..7=3 6..2=0x1C 1..0=3 +fmov.vv rd rs1 21..10=0 9..7=4 6..2=0x1C 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index 505a5e3..270663e 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -51,6 +51,7 @@ typelut[0x4B] = 8 typelut[0x4F] = 8 typelut[0x7B] = 4 typelut[0x2B] = 4 +typelut[0x73] = 3 opcode_base = 0 opcode_size = 7 |