diff options
| author |  Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2010-11-06 17:44:56 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2010-11-21 16:54:34 -0800 |
| commit | 0b707f09b7cc465505aebac30146932d10a45b6f (patch) | |
| tree | 8c67e107e2d7192b93526585e3ea581097a87dd0 | |
| parent | 54aec7dfe21f3ef0684a27f4545d668a20bce1f8 (diff) | |
[opcodes] generate latex and verilog correctly
| -rw-r--r-- | inst.v | 350 | ||||
| -rw-r--r-- | instr-table.tex | 1788 | ||||
| -rw-r--r-- | opcodes | 20 | ||||
| -rwxr-xr-x | parse-opcodes | 289 |
4 files changed, 1282 insertions, 1165 deletions
@@ -1,178 +1,178 @@ `define UNIMP 32'b00000000000000000000000000000000 `define J 32'b1100000_????????????????????????? `define JAL 32'b1100001_????????????????????????? -`define LUI 32'b1110001_?????_???????????????????? -`define JALR_C 32'b1110010_?????_?????_000_???????????? -`define JALR_R 32'b1110010_?????_?????_000_???????????? -`define JALR_J 32'b1110010_?????_?????_000_???????????? -`define BEQ 32'b1110011_?????_?????_000_000000000000 -`define BNE 32'b1110011_?????_?????_000_000000000000 -`define BLT 32'b1110011_?????_?????_000_000000000000 -`define BGE 32'b1110011_?????_?????_000_000000000000 -`define BLTU 32'b1110011_?????_?????_000_000000000000 -`define BGEU 32'b1110011_?????_?????_000_000000000000 -`define ADDI 32'b1110100_?????_?????_000_???????????? -`define SLTI 32'b1110100_?????_?????_000_???????????? -`define SLTIU 32'b1110100_?????_?????_000_???????????? -`define ANDI 32'b1110100_?????_?????_000_???????????? -`define ORI 32'b1110100_?????_?????_000_???????????? -`define XORI 32'b1110100_?????_?????_000_???????????? -`define SLLI 32'b1110100_?????_?????_000000000_?????? -`define SRLI 32'b1110100_?????_?????_000000000_?????? -`define SRAI 32'b1110100_?????_?????_000000000_?????? -`define ADD 32'b1110101_?????_?????_0000000000_????? -`define SUB 32'b1110101_?????_?????_0000000000_????? -`define SLT 32'b1110101_?????_?????_0000000000_????? -`define SLTU 32'b1110101_?????_?????_0000000000_????? -`define AND 32'b1110101_?????_?????_0000000000_????? -`define OR 32'b1110101_?????_?????_0000000000_????? -`define XOR 32'b1110101_?????_?????_0000000000_????? -`define NOR 32'b1110101_?????_?????_0000000000_????? -`define SLL 32'b1110101_?????_?????_0000000000_????? -`define SRL 32'b1110101_?????_?????_0000000000_????? -`define SRA 32'b1110101_?????_?????_0000000000_????? -`define MUL 32'b1110101_?????_?????_0000000000_????? -`define MULH 32'b1110101_?????_?????_0000000000_????? -`define MULHU 32'b1110101_?????_?????_0000000000_????? -`define DIV 32'b1110101_?????_?????_0000000000_????? -`define DIVU 32'b1110101_?????_?????_0000000000_????? -`define REM 32'b1110101_?????_?????_0000000000_????? -`define REMU 32'b1110101_?????_?????_0000000000_????? -`define ADDIW 32'b1110110_?????_?????_000_???????????? -`define SLLIW 32'b1110110_?????_?????_000000000_0_????? -`define SRLIW 32'b1110110_?????_?????_000000000_0_????? -`define SRAIW 32'b1110110_?????_?????_000000000_0_????? -`define ADDW 32'b1110111_?????_?????_0000000000_????? -`define SUBW 32'b1110111_?????_?????_0000000000_????? -`define SLLW 32'b1110111_?????_?????_0000000000_????? -`define SRLW 32'b1110111_?????_?????_0000000000_????? -`define SRAW 32'b1110111_?????_?????_0000000000_????? -`define MULW 32'b1110111_?????_?????_0000000000_????? -`define MULHW 32'b1110111_?????_?????_0000000000_????? -`define MULHUW 32'b1110111_?????_?????_0000000000_????? -`define DIVW 32'b1110111_?????_?????_0000000000_????? -`define DIVUW 32'b1110111_?????_?????_0000000000_????? -`define REMW 32'b1110111_?????_?????_0000000000_????? -`define REMUW 32'b1110111_?????_?????_0000000000_????? -`define LB 32'b1111000_?????_?????_000_???????????? -`define LH 32'b1111000_?????_?????_000_???????????? -`define LW 32'b1111000_?????_?????_000_???????????? -`define LD 32'b1111000_?????_?????_000_???????????? -`define LBU 32'b1111000_?????_?????_000_???????????? -`define LHU 32'b1111000_?????_?????_000_???????????? -`define LWU 32'b1111000_?????_?????_000_???????????? -`define SYNCI 32'b1111000_00000_?????_000_???????????? -`define SB 32'b1111001_?????_?????_000_000000000000 -`define SH 32'b1111001_?????_?????_000_000000000000 -`define SW 32'b1111001_?????_?????_000_000000000000 -`define SD 32'b1111001_?????_?????_000_000000000000 -`define AMOW_ADD 32'b1111010_?????_?????_0000000000_????? -`define AMOW_SWAP 32'b1111010_?????_?????_0000000000_????? -`define AMOW_AND 32'b1111010_?????_?????_0000000000_????? -`define AMOW_OR 32'b1111010_?????_?????_0000000000_????? -`define AMOW_MIN 32'b1111010_?????_?????_0000000000_????? -`define AMOW_MAX 32'b1111010_?????_?????_0000000000_????? -`define AMOW_MINU 32'b1111010_?????_?????_0000000000_????? -`define AMOW_MAXU 32'b1111010_?????_?????_0000000000_????? -`define AMO_ADD 32'b1111010_?????_?????_0000000000_????? -`define AMO_SWAP 32'b1111010_?????_?????_0000000000_????? -`define AMO_AND 32'b1111010_?????_?????_0000000000_????? -`define AMO_OR 32'b1111010_?????_?????_0000000000_????? -`define AMO_MIN 32'b1111010_?????_?????_0000000000_????? -`define AMO_MAX 32'b1111010_?????_?????_0000000000_????? -`define AMO_MINU 32'b1111010_?????_?????_0000000000_????? -`define AMO_MAXU 32'b1111010_?????_?????_0000000000_????? -`define RDNPC 32'b1111011_00000_00000_0000000000_????? -`define MFCR 32'b1111011_?????_00000_0000000000_????? -`define MTCR 32'b1111011_?????_?????_0000000000_00000 -`define SYNC 32'b1111011_00000_00000_0000000000_00000 -`define SYSCALL 32'b1111011_00000_00000_0000000000_00000 -`define EI 32'b1101011_00000_00000_0000000000_????? -`define DI 32'b1101011_00000_00000_0000000000_????? -`define MFPCR 32'b1101011_?????_00000_0000000000_????? -`define MTPCR 32'b1101011_?????_?????_0000000000_00000 -`define ERET 32'b1101011_00000_00000_0000000000_00000 -`define ADD_S 32'b1101010_?????_?????_0000000000_????? -`define SUB_S 32'b1101010_?????_?????_0000000000_????? -`define MUL_S 32'b1101010_?????_?????_0000000000_????? -`define DIV_S 32'b1101010_?????_?????_0000000000_????? -`define SQRT_S 32'b1101010_00000_?????_0000000000_????? -`define SGNINJ_S 32'b1101010_?????_?????_0000000000_????? -`define SGNINJN_S 32'b1101010_?????_?????_0000000000_????? -`define SGNMUL_S 32'b1101010_?????_?????_0000000000_????? -`define ADD_D 32'b1101010_?????_?????_0000000000_????? -`define SUB_D 32'b1101010_?????_?????_0000000000_????? -`define MUL_D 32'b1101010_?????_?????_0000000000_????? -`define DIV_D 32'b1101010_?????_?????_0000000000_????? -`define SQRT_D 32'b1101010_00000_?????_0000000000_????? -`define SGNINJ_D 32'b1101010_?????_?????_0000000000_????? -`define SGNINJN_D 32'b1101010_?????_?????_0000000000_????? -`define SGNMUL_D 32'b1101010_?????_?????_0000000000_????? -`define ADD_S_RM 32'b1101010_?????_?????_00_??_000000_????? -`define SUB_S_RM 32'b1101010_?????_?????_00_??_000000_????? -`define MUL_S_RM 32'b1101010_?????_?????_00_??_000000_????? -`define DIV_S_RM 32'b1101010_?????_?????_00_??_000000_????? -`define SQRT_S_RM 32'b1101010_00000_?????_00_??_000000_????? -`define ADD_D_RM 32'b1101010_?????_?????_00_??_000000_????? -`define SUB_D_RM 32'b1101010_?????_?????_00_??_000000_????? -`define MUL_D_RM 32'b1101010_?????_?????_00_??_000000_????? -`define DIV_D_RM 32'b1101010_?????_?????_00_??_000000_????? -`define SQRT_D_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVT_L_S_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVTU_L_S_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVT_W_S_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVTU_W_S_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVT_L_D_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVTU_L_D_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVT_W_D_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVTU_W_D_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVT_S_L 32'b1101010_00000_?????_0000000000_????? -`define CVTU_S_L 32'b1101010_00000_?????_0000000000_????? -`define CVT_S_W 32'b1101010_00000_?????_0000000000_????? -`define CVTU_S_W 32'b1101010_00000_?????_0000000000_????? -`define CVT_D_L 32'b1101010_00000_?????_0000000000_????? -`define CVTU_D_L 32'b1101010_00000_?????_0000000000_????? -`define CVT_D_W 32'b1101010_00000_?????_0000000000_????? -`define CVTU_D_W 32'b1101010_00000_?????_0000000000_????? -`define CVT_S_L_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVTU_S_L_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVT_S_W_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVTU_S_W_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVT_D_L_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVTU_D_L_RM 32'b1101010_00000_?????_00_??_000000_????? -`define CVT_S_D 32'b1101010_00000_?????_0000000000_????? -`define CVT_D_S 32'b1101010_00000_?????_0000000000_????? -`define CVT_S_D_RM 32'b1101010_00000_?????_00_??_000000_????? -`define C_EQ_S 32'b1101010_?????_?????_0000000000_????? -`define C_LT_S 32'b1101010_?????_?????_0000000000_????? -`define C_LE_S 32'b1101010_?????_?????_0000000000_????? -`define C_EQ_D 32'b1101010_?????_?????_0000000000_????? -`define C_LT_D 32'b1101010_?????_?????_0000000000_????? -`define C_LE_D 32'b1101010_?????_?????_0000000000_????? -`define MFF_S 32'b1101010_?????_00000_0000000000_????? -`define MFF_D 32'b1101010_?????_00000_0000000000_????? -`define MFFL_D 32'b1101010_?????_00000_0000000000_????? -`define MFFH_D 32'b1101010_?????_00000_0000000000_????? -`define MTF_S 32'b1101010_00000_?????_0000000000_????? -`define MTF_D 32'b1101010_00000_?????_0000000000_????? -`define MTFLH_D 32'b1101010_?????_?????_0000000000_????? -`define L_S 32'b1101000_?????_?????_000_???????????? -`define L_D 32'b1101000_?????_?????_000_???????????? -`define S_S 32'b1101001_?????_?????_000_000000000000 -`define S_D 32'b1101001_?????_?????_000_000000000000 -`define MADD_S 32'b1101100_?????_?????_00000_?????_????? -`define MSUB_S 32'b1101101_?????_?????_00000_?????_????? -`define NMSUB_S 32'b1101110_?????_?????_00000_?????_????? -`define NMADD_S 32'b1101111_?????_?????_00000_?????_????? -`define MADD_D 32'b1101100_?????_?????_00000_?????_????? -`define MSUB_D 32'b1101101_?????_?????_00000_?????_????? -`define NMSUB_D 32'b1101110_?????_?????_00000_?????_????? -`define NMADD_D 32'b1101111_?????_?????_00000_?????_????? -`define MADD_S_RM 32'b1101100_?????_?????_00_??_0_?????_????? -`define MSUB_S_RM 32'b1101101_?????_?????_00_??_0_?????_????? -`define NMSUB_S_RM 32'b1101110_?????_?????_00_??_0_?????_????? -`define NMADD_S_RM 32'b1101111_?????_?????_00_??_0_?????_????? -`define MADD_D_RM 32'b1101100_?????_?????_00_??_0_?????_????? -`define MSUB_D_RM 32'b1101101_?????_?????_00_??_0_?????_????? -`define NMSUB_D_RM 32'b1101110_?????_?????_00_??_0_?????_????? -`define NMADD_D_RM 32'b1101111_?????_?????_00_??_0_?????_????? +`define JALR_C 32'b1100010_000_????????????_?????_????? +`define JALR_R 32'b1100010_001_????????????_?????_????? +`define JALR_J 32'b1100010_010_????????????_?????_????? +`define BEQ 32'b1100011_000_???????_?????_?????_????? +`define BNE 32'b1100011_001_???????_?????_?????_????? +`define BLT 32'b1100011_100_???????_?????_?????_????? +`define BGE 32'b1100011_101_???????_?????_?????_????? +`define BLTU 32'b1100011_110_???????_?????_?????_????? +`define BGEU 32'b1100011_111_???????_?????_?????_????? +`define LUI 32'b1110001_????????????????????_????? +`define ADDI 32'b1110100_000_????????????_?????_????? +`define SLTI 32'b1110100_010_????????????_?????_????? +`define SLTIU 32'b1110100_011_????????????_?????_????? +`define ANDI 32'b1110100_100_????????????_?????_????? +`define ORI 32'b1110100_101_????????????_?????_????? +`define XORI 32'b1110100_110_????????????_?????_????? +`define SLLI 32'b1110100_111_000001_??????_?????_????? +`define SRLI 32'b1110100_111_000010_??????_?????_????? +`define SRAI 32'b1110100_111_000011_??????_?????_????? +`define ADD 32'b1110101_0000000000_?????_?????_????? +`define SUB 32'b1110101_0000000001_?????_?????_????? +`define SLT 32'b1110101_0000000010_?????_?????_????? +`define SLTU 32'b1110101_0000000011_?????_?????_????? +`define AND 32'b1110101_0000000100_?????_?????_????? +`define OR 32'b1110101_0000000101_?????_?????_????? +`define XOR 32'b1110101_0000000110_?????_?????_????? +`define NOR 32'b1110101_0000000111_?????_?????_????? +`define SLL 32'b1110101_1110000010_?????_?????_????? +`define SRL 32'b1110101_1110000100_?????_?????_????? +`define SRA 32'b1110101_1110000110_?????_?????_????? +`define MUL 32'b1110101_0010000000_?????_?????_????? +`define MULH 32'b1110101_0010000010_?????_?????_????? +`define MULHU 32'b1110101_0010000011_?????_?????_????? +`define DIV 32'b1110101_0010000100_?????_?????_????? +`define DIVU 32'b1110101_0010000101_?????_?????_????? +`define REM 32'b1110101_0010000110_?????_?????_????? +`define REMU 32'b1110101_0010000111_?????_?????_????? +`define ADDIW 32'b1110110_000_????????????_?????_????? +`define SLLIW 32'b1110110_111_000001_0_?????_?????_????? +`define SRLIW 32'b1110110_111_000010_0_?????_?????_????? +`define SRAIW 32'b1110110_111_000011_0_?????_?????_????? +`define ADDW 32'b1110111_0000000000_?????_?????_????? +`define SUBW 32'b1110111_0000000001_?????_?????_????? +`define SLLW 32'b1110111_1110000010_?????_?????_????? +`define SRLW 32'b1110111_1110000100_?????_?????_????? +`define SRAW 32'b1110111_1110000110_?????_?????_????? +`define MULW 32'b1110111_0010000000_?????_?????_????? +`define MULHW 32'b1110111_0010000010_?????_?????_????? +`define MULHUW 32'b1110111_0010000011_?????_?????_????? +`define DIVW 32'b1110111_0010000100_?????_?????_????? +`define DIVUW 32'b1110111_0010000101_?????_?????_????? +`define REMW 32'b1110111_0010000110_?????_?????_????? +`define REMUW 32'b1110111_0010000111_?????_?????_????? +`define LB 32'b1111000_000_????????????_?????_????? +`define LH 32'b1111000_001_????????????_?????_????? +`define LW 32'b1111000_010_????????????_?????_????? +`define LD 32'b1111000_011_????????????_?????_????? +`define LBU 32'b1111000_100_????????????_?????_????? +`define LHU 32'b1111000_101_????????????_?????_????? +`define LWU 32'b1111000_110_????????????_?????_????? +`define SYNCI 32'b1111000_111_????????????_?????_00000 +`define SB 32'b1111001_000_???????_?????_?????_????? +`define SH 32'b1111001_001_???????_?????_?????_????? +`define SW 32'b1111001_010_???????_?????_?????_????? +`define SD 32'b1111001_011_???????_?????_?????_????? +`define AMOW_ADD 32'b1111010_0100000000_?????_?????_????? +`define AMOW_SWAP 32'b1111010_0100000001_?????_?????_????? +`define AMOW_AND 32'b1111010_0100000010_?????_?????_????? +`define AMOW_OR 32'b1111010_0100000011_?????_?????_????? +`define AMOW_MIN 32'b1111010_0100000100_?????_?????_????? +`define AMOW_MAX 32'b1111010_0100000101_?????_?????_????? +`define AMOW_MINU 32'b1111010_0100000110_?????_?????_????? +`define AMOW_MAXU 32'b1111010_0100000111_?????_?????_????? +`define AMO_ADD 32'b1111010_0110000000_?????_?????_????? +`define AMO_SWAP 32'b1111010_0110000001_?????_?????_????? +`define AMO_AND 32'b1111010_0110000010_?????_?????_????? +`define AMO_OR 32'b1111010_0110000011_?????_?????_????? +`define AMO_MIN 32'b1111010_0110000100_?????_?????_????? +`define AMO_MAX 32'b1111010_0110000101_?????_?????_????? +`define AMO_MINU 32'b1111010_0110000110_?????_?????_????? +`define AMO_MAXU 32'b1111010_0110000111_?????_?????_????? +`define RDNPC 32'b1111011_0000000000_00000_00000_????? +`define MFCR 32'b1111011_0010000000_?????_00000_????? +`define MTCR 32'b1111011_0010000001_?????_?????_00000 +`define SYNC 32'b1111011_0100000000_00000_00000_00000 +`define SYSCALL 32'b1111011_0110000000_00000_00000_00000 +`define EI 32'b1101011_0000000000_00000_00000_????? +`define DI 32'b1101011_0000000001_00000_00000_????? +`define MFPCR 32'b1101011_0010000000_?????_00000_????? +`define MTPCR 32'b1101011_0010000001_?????_?????_00000 +`define ERET 32'b1101011_0100000000_00000_00000_00000 +`define ADD_S 32'b1101010_0000000000_?????_?????_????? +`define SUB_S 32'b1101010_0000000001_?????_?????_????? +`define MUL_S 32'b1101010_0000000010_?????_?????_????? +`define DIV_S 32'b1101010_0000000011_?????_?????_????? +`define SQRT_S 32'b1101010_0000000100_00000_?????_????? +`define SGNINJ_S 32'b1101010_0000000101_?????_?????_????? +`define SGNINJN_S 32'b1101010_0000000110_?????_?????_????? +`define SGNMUL_S 32'b1101010_0000000111_?????_?????_????? +`define ADD_D 32'b1101010_1100000000_?????_?????_????? +`define SUB_D 32'b1101010_1100000001_?????_?????_????? +`define MUL_D 32'b1101010_1100000010_?????_?????_????? +`define DIV_D 32'b1101010_1100000011_?????_?????_????? +`define SQRT_D 32'b1101010_1100000100_00000_?????_????? +`define SGNINJ_D 32'b1101010_1100000101_?????_?????_????? +`define SGNINJN_D 32'b1101010_1100000110_?????_?????_????? +`define SGNMUL_D 32'b1101010_1100000111_?????_?????_????? +`define ADD_S_RM 32'b1101010_001_??_00000_?????_?????_????? +`define SUB_S_RM 32'b1101010_001_??_00001_?????_?????_????? +`define MUL_S_RM 32'b1101010_001_??_00010_?????_?????_????? +`define DIV_S_RM 32'b1101010_001_??_00011_?????_?????_????? +`define SQRT_S_RM 32'b1101010_001_??_00100_00000_?????_????? +`define ADD_D_RM 32'b1101010_111_??_00000_?????_?????_????? +`define SUB_D_RM 32'b1101010_111_??_00001_?????_?????_????? +`define MUL_D_RM 32'b1101010_111_??_00010_?????_?????_????? +`define DIV_D_RM 32'b1101010_111_??_00011_?????_?????_????? +`define SQRT_D_RM 32'b1101010_111_??_00100_00000_?????_????? +`define CVT_L_S_RM 32'b1101010_001_??_01000_00000_?????_????? +`define CVTU_L_S_RM 32'b1101010_001_??_01001_00000_?????_????? +`define CVT_W_S_RM 32'b1101010_001_??_01010_00000_?????_????? +`define CVTU_W_S_RM 32'b1101010_001_??_01011_00000_?????_????? +`define CVT_L_D_RM 32'b1101010_111_??_01000_00000_?????_????? +`define CVTU_L_D_RM 32'b1101010_111_??_01001_00000_?????_????? +`define CVT_W_D_RM 32'b1101010_111_??_01010_00000_?????_????? +`define CVTU_W_D_RM 32'b1101010_111_??_01011_00000_?????_????? +`define CVT_S_L 32'b1101010_0000001100_00000_?????_????? +`define CVTU_S_L 32'b1101010_0000001101_00000_?????_????? +`define CVT_S_W 32'b1101010_0000001110_00000_?????_????? +`define CVTU_S_W 32'b1101010_0000001111_00000_?????_????? +`define CVT_D_L 32'b1101010_1100001100_00000_?????_????? +`define CVTU_D_L 32'b1101010_1100001101_00000_?????_????? +`define CVT_D_W 32'b1101010_1100001110_00000_?????_????? +`define CVTU_D_W 32'b1101010_1100001111_00000_?????_????? +`define CVT_S_L_RM 32'b1101010_001_??_01100_00000_?????_????? +`define CVTU_S_L_RM 32'b1101010_001_??_01101_00000_?????_????? +`define CVT_S_W_RM 32'b1101010_001_??_01110_00000_?????_????? +`define CVTU_S_W_RM 32'b1101010_001_??_01111_00000_?????_????? +`define CVT_D_L_RM 32'b1101010_111_??_01100_00000_?????_????? +`define CVTU_D_L_RM 32'b1101010_111_??_01101_00000_?????_????? +`define CVT_S_D 32'b1101010_0000010011_00000_?????_????? +`define CVT_D_S 32'b1101010_1100010000_00000_?????_????? +`define CVT_S_D_RM 32'b1101010_001_??_10011_00000_?????_????? +`define C_EQ_S 32'b1101010_0000010101_?????_?????_????? +`define C_LT_S 32'b1101010_0000010110_?????_?????_????? +`define C_LE_S 32'b1101010_0000010111_?????_?????_????? +`define C_EQ_D 32'b1101010_1100010101_?????_?????_????? +`define C_LT_D 32'b1101010_1100010110_?????_?????_????? +`define C_LE_D 32'b1101010_1100010111_?????_?????_????? +`define MFF_S 32'b1101010_0001011000_?????_00000_????? +`define MFF_D 32'b1101010_1101011000_?????_00000_????? +`define MFFL_D 32'b1101010_1101011001_?????_00000_????? +`define MFFH_D 32'b1101010_1101011010_?????_00000_????? +`define MTF_S 32'b1101010_0001011100_00000_?????_????? +`define MTF_D 32'b1101010_1101011100_00000_?????_????? +`define MTFLH_D 32'b1101010_1101111100_?????_?????_????? +`define L_S 32'b1101000_010_????????????_?????_????? +`define L_D 32'b1101000_011_????????????_?????_????? +`define S_S 32'b1101001_010_???????_?????_?????_????? +`define S_D 32'b1101001_011_???????_?????_?????_????? +`define MADD_S 32'b1101100_000_00_?????_?????_?????_????? +`define MSUB_S 32'b1101101_000_00_?????_?????_?????_????? +`define NMSUB_S 32'b1101110_000_00_?????_?????_?????_????? +`define NMADD_S 32'b1101111_000_00_?????_?????_?????_????? +`define MADD_D 32'b1101100_110_00_?????_?????_?????_????? +`define MSUB_D 32'b1101101_110_00_?????_?????_?????_????? +`define NMSUB_D 32'b1101110_110_00_?????_?????_?????_????? +`define NMADD_D 32'b1101111_110_00_?????_?????_?????_????? +`define MADD_S_RM 32'b1101100_001_??_?????_?????_?????_????? +`define MSUB_S_RM 32'b1101101_001_??_?????_?????_?????_????? +`define NMSUB_S_RM 32'b1101110_001_??_?????_?????_?????_????? +`define NMADD_S_RM 32'b1101111_001_??_?????_?????_?????_????? +`define MADD_D_RM 32'b1101100_111_??_?????_?????_?????_????? +`define MSUB_D_RM 32'b1101101_111_??_?????_?????_?????_????? +`define NMSUB_D_RM 32'b1101110_111_??_?????_?????_?????_????? +`define NMADD_D_RM 32'b1101111_111_??_?????_?????_?????_????? diff --git a/instr-table.tex b/instr-table.tex index 5455df7..4a4479e 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -18,446 +18,442 @@ \hspace*{0.1in} & \hspace*{0.5in} \\ & -\instbitrange{31}{27} & -\instbitrange{26}{25} & -\instbitrange{24}{20} & -\instbitrange{19}{15} & -\instbitrange{14}{13} & -\instbit{12} & -\instbit{11} & -\instbit{10} & -\instbitrange{9}{6} & -\instbit{5} & +\instbitrange{31}{25} & +\instbitrange{24}{22} & +\instbitrange{21}{20} & +\instbitrange{19}{16} & +\instbit{15} & +\instbitrange{14}{10} & +\instbitrange{9}{5} & \instbitrange{4}{0} \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{1}{|c|}{opcode5} & -\multicolumn{10}{c|}{jump target} & J-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{7}{c|}{jump target} & J-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & LUI-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{6}{c|}{LUI-immediate} & +\multicolumn{1}{c|}{rd} & LUI-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd/rs2} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{5}{c|}{immediate} & I-type \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & I-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{3}{c|}{immed[11:5]} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{funct9} & -\multicolumn{2}{c|}{shamt} & ISH-type \\ -\cline{2-12} +\multicolumn{1}{c|}{immed[4:0]} & B-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{4}{c|}{funct10} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{funct10} & \multicolumn{1}{c|}{rd} & R-type \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{2}{c|}{funct5} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{funct5} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & R4-type \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Unimplemented Instruction} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{11}{|c|}{00000000000000000000000000000000} & UNIMP \\ -\cline{2-12} +\multicolumn{8}{|c|}{00000000000000000000000000000000} & UNIMP \\ +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Control Transfer Instructions} & \\ -\cline{2-12} +\cline{2-9} & \multicolumn{1}{|c|}{1100000} & -\multicolumn{10}{c|}{imm25} & J imm25 \\ -\cline{2-12} - - -& -\multicolumn{2}{|c|}{1111011} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{6}{c|}{0000000000} & -\multicolumn{1}{c|}{rd} & RDNPC rd \\ -\cline{2-12} +\multicolumn{7}{c|}{imm25} & J imm25 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111011} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{00000} & -\multicolumn{6}{c|}{0000000000} & -\multicolumn{1}{c|}{rd} & MFCR rd,rs2 \\ -\cline{2-12} +\multicolumn{1}{|c|}{1100001} & +\multicolumn{7}{c|}{imm25} & JAL imm25 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111011} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{1100010} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & -\multicolumn{1}{c|}{00000} & MTCR rs1,rs2 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & JALR.C rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111011} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{6}{c|}{0000000000} & -\multicolumn{1}{c|}{00000} & SYNC \\ -\cline{2-12} +\multicolumn{1}{|c|}{1100010} & +\multicolumn{1}{c|}{001} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & JALR.R rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111011} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{6}{c|}{0000000000} & -\multicolumn{1}{c|}{00000} & SYSCALL imm12 \\ -\cline{2-12} +\multicolumn{1}{|c|}{1100010} & +\multicolumn{1}{c|}{010} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & JALR.J rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{|c|}{1100011} & +\multicolumn{1}{c|}{000} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & BEQ rs1,rs2,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & BEQ rs1,rs2,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{|c|}{1100011} & +\multicolumn{1}{c|}{001} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & BNE rs1,rs2,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & BNE rs1,rs2,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{|c|}{1100011} & +\multicolumn{1}{c|}{100} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & BLT rs1,rs2,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & BLT rs1,rs2,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{|c|}{1100011} & +\multicolumn{1}{c|}{101} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & BGE rs1,rs2,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & BGE rs1,rs2,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{|c|}{1100011} & +\multicolumn{1}{c|}{110} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & BLTU rs1,rs2,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & BLTU rs1,rs2,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{|c|}{1100011} & +\multicolumn{1}{c|}{111} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & BGEU rs1,rs2,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & BGEU rs1,rs2,imm12lo,imm12hi \\ +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Memory Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & LB rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & LB rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{c|}{001} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & LH rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & LH rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{c|}{010} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & LW rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & LW rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{c|}{011} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & LD rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & LD rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{c|}{100} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & LBU rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & LBU rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{c|}{101} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & LHU rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & LHU rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{c|}{110} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & LWU rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & LWU rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111000} & -\multicolumn{1}{c|}{00000} & +\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{c|}{111} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & SYNCI rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{00000} & SYNCI rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111001} & +\multicolumn{1}{|c|}{1111001} & +\multicolumn{1}{c|}{000} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & SB rs2,rs1,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & SB rs2,rs1,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111001} & +\multicolumn{1}{|c|}{1111001} & +\multicolumn{1}{c|}{001} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & SH rs2,rs1,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & SH rs2,rs1,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111001} & +\multicolumn{1}{|c|}{1111001} & +\multicolumn{1}{c|}{010} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & SW rs2,rs1,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & SW rs2,rs1,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1111001} & +\multicolumn{1}{|c|}{1111001} & +\multicolumn{1}{c|}{011} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & SD rs2,rs1,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & SD rs2,rs1,imm12lo,imm12hi \\ +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Atomic Memory Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0100000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMOW.ADD rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0100000001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMOW.SWAP rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0100000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMOW.AND rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0100000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMOW.OR rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0100000100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMOW.MIN rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0100000101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMOW.MAX rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0100000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMOW.MINU rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0100000111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMOW.MAXU rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0110000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMO.ADD rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0110000001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMO.SWAP rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0110000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMO.AND rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0110000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMO.OR rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0110000100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMO.MIN rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0110000101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMO.MAX rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0110000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMO.MINU rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{|c|}{1111010} & +\multicolumn{4}{c|}{0110000111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AMO.MAXU rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} \end{tabular} @@ -487,467 +483,471 @@ \hspace*{0.1in} & \hspace*{0.5in} \\ & -\instbitrange{31}{27} & -\instbitrange{26}{25} & -\instbitrange{24}{20} & -\instbitrange{19}{15} & -\instbitrange{14}{13} & -\instbit{12} & -\instbit{11} & -\instbit{10} & -\instbitrange{9}{6} & -\instbit{5} & +\instbitrange{31}{25} & +\instbitrange{24}{22} & +\instbitrange{21}{20} & +\instbitrange{19}{16} & +\instbit{15} & +\instbitrange{14}{10} & +\instbitrange{9}{5} & \instbitrange{4}{0} \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{1}{|c|}{opcode5} & -\multicolumn{10}{c|}{jump target} & J-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{7}{c|}{jump target} & J-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & LUI-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{6}{c|}{LUI-immediate} & +\multicolumn{1}{c|}{rd} & LUI-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd/rs2} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{5}{c|}{immediate} & I-type \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & I-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{3}{c|}{immed[11:5]} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{funct9} & -\multicolumn{2}{c|}{shamt} & ISH-type \\ -\cline{2-12} +\multicolumn{1}{c|}{immed[4:0]} & B-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{4}{c|}{funct10} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{funct10} & \multicolumn{1}{c|}{rd} & R-type \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{2}{c|}{funct5} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{funct5} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & R4-type \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Integer Compute Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110001} & -\multicolumn{1}{c|}{rd} & -\multicolumn{8}{c|}{imm20} & LUI rd,imm20 \\ -\cline{2-12} +\multicolumn{1}{|c|}{1110001} & +\multicolumn{6}{c|}{imm20} & +\multicolumn{1}{c|}{rd} & LUI rd,imm20 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & ADDI rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & ADDI rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{010} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & SLTI rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & SLTI rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{011} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & SLTIU rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & SLTIU rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{100} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & ANDI rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & ANDI rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{101} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & ORI rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & ORI rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{110} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & XORI rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & XORI rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{111} & +\multicolumn{2}{c|}{000001} & +\multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{000000000} & -\multicolumn{2}{c|}{shamt} & SLLI rd,rs1,shamt \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & SLLI rd,rs1,shamt \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{111} & +\multicolumn{2}{c|}{000010} & +\multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{000000000} & -\multicolumn{2}{c|}{shamt} & SRLI rd,rs1,shamt \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & SRLI rd,rs1,shamt \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110100} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110100} & +\multicolumn{1}{c|}{111} & +\multicolumn{2}{c|}{000011} & +\multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{000000000} & -\multicolumn{2}{c|}{shamt} & SRAI rd,rs1,shamt \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & SRAI rd,rs1,shamt \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & ADD rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0000000001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SUB rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SLT rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0000000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SLTU rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0000000100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & AND rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0000000101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & OR rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0000000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & XOR rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0000000111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & NOR rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{1110000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SLL rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{1110000100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SRL rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{1110000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SRA rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0010000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MUL rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0010000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MULH rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0010000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MULHU rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0010000100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & DIV rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0010000101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & DIVU rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0010000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & REM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{|c|}{1110101} & +\multicolumn{4}{c|}{0010000111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & REMU rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf 32-bit Integer Compute Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110110} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1110110} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & ADDIW rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & ADDIW rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110110} & -\multicolumn{1}{c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{000000000} & +\multicolumn{1}{|c|}{1110110} & +\multicolumn{1}{c|}{111} & +\multicolumn{2}{c|}{000001} & \multicolumn{1}{c|}{0} & -\multicolumn{1}{c|}{shamtw} & SLLIW rd,rs1,shamtw \\ -\cline{2-12} +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rs1} & SLLIW rd,rs1,shamtw \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110110} & -\multicolumn{1}{c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{000000000} & +\multicolumn{1}{|c|}{1110110} & +\multicolumn{1}{c|}{111} & +\multicolumn{2}{c|}{000010} & \multicolumn{1}{c|}{0} & -\multicolumn{1}{c|}{shamtw} & SRLIW rd,rs1,shamtw \\ -\cline{2-12} +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rs1} & SRLIW rd,rs1,shamtw \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110110} & -\multicolumn{1}{c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{000000000} & +\multicolumn{1}{|c|}{1110110} & +\multicolumn{1}{c|}{111} & +\multicolumn{2}{c|}{000011} & \multicolumn{1}{c|}{0} & -\multicolumn{1}{c|}{shamtw} & SRAIW rd,rs1,shamtw \\ -\cline{2-12} +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rs1} & SRAIW rd,rs1,shamtw \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & ADDW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0000000001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SUBW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{1110000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SLLW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{1110000100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SRLW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{1110000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SRAW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0010000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MULW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0010000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MULHW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0010000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MULHUW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0010000100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & DIVW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0010000101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & DIVUW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0010000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & REMW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{|c|}{1110111} & +\multicolumn{4}{c|}{0010000111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & REMUW rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} \end{tabular} @@ -977,482 +977,474 @@ \hspace*{0.1in} & \hspace*{0.5in} \\ & -\instbitrange{31}{27} & -\instbitrange{26}{25} & -\instbitrange{24}{20} & -\instbitrange{19}{15} & -\instbitrange{14}{13} & -\instbit{12} & -\instbit{11} & -\instbit{10} & -\instbitrange{9}{6} & -\instbit{5} & +\instbitrange{31}{25} & +\instbitrange{24}{22} & +\instbitrange{21}{20} & +\instbitrange{19}{16} & +\instbit{15} & +\instbitrange{14}{10} & +\instbitrange{9}{5} & \instbitrange{4}{0} \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{1}{|c|}{opcode5} & -\multicolumn{10}{c|}{jump target} & J-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{7}{c|}{jump target} & J-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & LUI-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{6}{c|}{LUI-immediate} & +\multicolumn{1}{c|}{rd} & LUI-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd/rs2} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{5}{c|}{immediate} & I-type \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & I-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{3}{c|}{immed[11:5]} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{funct9} & -\multicolumn{2}{c|}{shamt} & ISH-type \\ -\cline{2-12} +\multicolumn{1}{c|}{immed[4:0]} & B-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{4}{c|}{funct10} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{funct10} & \multicolumn{1}{c|}{rd} & R-type \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{2}{c|}{funct5} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{funct5} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & R4-type \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Floating-Point Memory Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1101000} & +\multicolumn{1}{c|}{010} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & L.S rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & L.S rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1101000} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{1101000} & +\multicolumn{1}{c|}{011} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{imm12} & L.D rd,rs1,imm12 \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & L.D rd,rs1,imm12 \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1101001} & +\multicolumn{1}{|c|}{1101001} & +\multicolumn{1}{c|}{010} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & S.S rs2,rs1,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & S.S rs2,rs1,imm12lo,imm12hi \\ +\cline{2-9} & -\multicolumn{2}{|c|}{1101001} & +\multicolumn{1}{|c|}{1101001} & +\multicolumn{1}{c|}{011} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000} & -\multicolumn{5}{c|}{000000000000} & S.D rs2,rs1,imm12lo,imm12hi \\ -\cline{2-12} +\multicolumn{1}{c|}{imm12lo} & S.D rs2,rs1,imm12lo,imm12hi \\ +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Floating-Point Compute Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & ADD.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000000001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SUB.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MUL.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & DIV.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000000100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SQRT.S rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & ADD.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100000001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SUB.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MUL.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & DIV.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100000100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SQRT.D rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101100} & +\multicolumn{1}{|c|}{1101100} & +\multicolumn{2}{c|}{00000} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{00000} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & MADD.S rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101101} & +\multicolumn{1}{|c|}{1101101} & +\multicolumn{2}{c|}{00000} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{00000} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & MSUB.S rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101110} & +\multicolumn{1}{|c|}{1101110} & +\multicolumn{2}{c|}{00000} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{00000} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & NMSUB.S rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101111} & +\multicolumn{1}{|c|}{1101111} & +\multicolumn{2}{c|}{00000} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{00000} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & NMADD.S rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101100} & +\multicolumn{1}{|c|}{1101100} & +\multicolumn{2}{c|}{11000} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{00000} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & MADD.D rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101101} & +\multicolumn{1}{|c|}{1101101} & +\multicolumn{2}{c|}{11000} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{00000} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & MSUB.D rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101110} & +\multicolumn{1}{|c|}{1101110} & +\multicolumn{2}{c|}{11000} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{00000} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & NMSUB.D rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101111} & +\multicolumn{1}{|c|}{1101111} & +\multicolumn{2}{c|}{11000} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{00000} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & NMADD.D rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & ADD.S.RM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & SUB.S.RM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & MUL.S.RM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & DIV.S.RM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & SQRT.S.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & ADD.D.RM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & SUB.D.RM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & MUL.D.RM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & DIV.D.RM rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{00100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & SQRT.D.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101100} & +\multicolumn{1}{|c|}{1101100} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{0} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & MADD.S.RM rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101101} & +\multicolumn{1}{|c|}{1101101} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{0} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & MSUB.S.RM rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101110} & +\multicolumn{1}{|c|}{1101110} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{0} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & NMSUB.S.RM rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101111} & +\multicolumn{1}{|c|}{1101111} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{0} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & NMADD.S.RM rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101100} & +\multicolumn{1}{|c|}{1101100} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{0} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & MADD.D.RM rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101101} & +\multicolumn{1}{|c|}{1101101} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{0} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & MSUB.D.RM rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101110} & +\multicolumn{1}{|c|}{1101110} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{0} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & NMSUB.D.RM rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101111} & +\multicolumn{1}{|c|}{1101111} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{0} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & NMADD.D.RM rd,rs1,rs2,rs3 \\ -\cline{2-12} +\cline{2-9} \end{tabular} @@ -1482,449 +1474,447 @@ \hspace*{0.1in} & \hspace*{0.5in} \\ & -\instbitrange{31}{27} & -\instbitrange{26}{25} & -\instbitrange{24}{20} & -\instbitrange{19}{15} & -\instbitrange{14}{13} & -\instbit{12} & -\instbit{11} & -\instbit{10} & -\instbitrange{9}{6} & -\instbit{5} & +\instbitrange{31}{25} & +\instbitrange{24}{22} & +\instbitrange{21}{20} & +\instbitrange{19}{16} & +\instbit{15} & +\instbitrange{14}{10} & +\instbitrange{9}{5} & \instbitrange{4}{0} \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{1}{|c|}{opcode5} & -\multicolumn{10}{c|}{jump target} & J-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{7}{c|}{jump target} & J-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & LUI-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{6}{c|}{LUI-immediate} & +\multicolumn{1}{c|}{rd} & LUI-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd/rs2} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{5}{c|}{immediate} & I-type \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & I-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{3}{c|}{immed[11:5]} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{funct9} & -\multicolumn{2}{c|}{shamt} & ISH-type \\ -\cline{2-12} +\multicolumn{1}{c|}{immed[4:0]} & B-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{4}{c|}{funct10} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{funct10} & \multicolumn{1}{c|}{rd} & R-type \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{2}{c|}{funct5} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{funct5} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & R4-type \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Floating-Point Move \& Conversion Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000000101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SGNINJ.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SGNINJN.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000000111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SGNMUL.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100000101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SGNINJ.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100000110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SGNINJN.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100000111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & SGNMUL.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000010011} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVT.S.D rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100010000} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVT.D.S rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{10011} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVT.S.D.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Integer to Floating-Point Move \& Conversion Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000001100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVT.S.L rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000001101} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVTU.S.L rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000001110} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVT.S.W rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000001111} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVTU.S.W rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100001100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVT.D.L rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100001101} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVTU.D.L rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100001110} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVT.D.W rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100001111} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & CVTU.D.W rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVT.S.L.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01101} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVTU.S.L.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01110} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVT.S.W.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01111} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVTU.S.W.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVT.D.L.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01101} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVTU.D.L.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1101111100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MTFLH.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0001011100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MTF.S rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1101011100} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MTF.D rd,rs1 \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Floating-Point to Integer Move \& Conversion Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01000} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVT.L.S.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVTU.L.S.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01010} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVT.W.S.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01011} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVTU.W.S.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01000} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVT.L.D.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVTU.L.D.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01010} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVT.W.D.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rm} & +\multicolumn{2}{c|}{01011} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00} & -\multicolumn{2}{c|}{rm} & -\multicolumn{3}{c|}{000000} & \multicolumn{1}{c|}{rd} & CVTU.W.D.RM rd,rs1 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1101011001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{00000} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MFFL.D rd,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1101011010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{00000} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MFFH.D rd,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0001011000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{00000} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MFF.S rd,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1101011000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{00000} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & MFF.D rd,rs2 \\ -\cline{2-12} +\cline{2-9} \end{tabular} @@ -1954,131 +1944,219 @@ \hspace*{0.1in} & \hspace*{0.5in} \\ & -\instbitrange{31}{27} & -\instbitrange{26}{25} & -\instbitrange{24}{20} & -\instbitrange{19}{15} & -\instbitrange{14}{13} & -\instbit{12} & -\instbit{11} & -\instbit{10} & -\instbitrange{9}{6} & -\instbit{5} & +\instbitrange{31}{25} & +\instbitrange{24}{22} & +\instbitrange{21}{20} & +\instbitrange{19}{16} & +\instbit{15} & +\instbitrange{14}{10} & +\instbitrange{9}{5} & \instbitrange{4}{0} \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{1}{|c|}{opcode5} & -\multicolumn{10}{c|}{jump target} & J-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{7}{c|}{jump target} & J-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & LUI-type \\ -\cline{2-12} +\multicolumn{1}{|c|}{opcode} & +\multicolumn{6}{c|}{LUI-immediate} & +\multicolumn{1}{c|}{rd} & LUI-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd/rs2} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{5}{c|}{immediate} & I-type \\ -\cline{2-12} +\multicolumn{1}{c|}{rd} & I-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & -\multicolumn{1}{c|}{rd} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{3}{c|}{immed[11:5]} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{funct9} & -\multicolumn{2}{c|}{shamt} & ISH-type \\ -\cline{2-12} +\multicolumn{1}{c|}{immed[4:0]} & B-type \\ +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{4}{c|}{funct10} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{funct10} & \multicolumn{1}{c|}{rd} & R-type \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{2}{c|}{funct5} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{funct5} & -\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rd} & R4-type \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Floating-Point Compare Instructions} & \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000010101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & C.EQ.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000010110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & C.LT.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{0000010111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & C.LE.S rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100010101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & C.EQ.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100010110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & C.LT.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & -\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{|c|}{1101010} & +\multicolumn{4}{c|}{1100010111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{6}{c|}{0000000000} & \multicolumn{1}{c|}{rd} & C.LE.D rd,rs1,rs2 \\ -\cline{2-12} +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Miscellaneous Instructions} & \\ -\cline{2-12} +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1111011} & +\multicolumn{4}{c|}{0000000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & RDNPC rd \\ +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1111011} & +\multicolumn{4}{c|}{0010000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & MFCR rd,rs2 \\ +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1111011} & +\multicolumn{4}{c|}{0010000001} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & MTCR rs1,rs2 \\ +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1111011} & +\multicolumn{4}{c|}{0100000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & SYNC \\ +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1111011} & +\multicolumn{4}{c|}{0110000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & SYSCALL imm12 \\ +\cline{2-9} & \multicolumn{11}{c}{} & \\ & \multicolumn{11}{c}{\bf Privileged Instructions} & \\ -\cline{2-12} +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1101011} & +\multicolumn{4}{c|}{0000000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & EI rd \\ +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1101011} & +\multicolumn{4}{c|}{0000000001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & DI rd \\ +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1101011} & +\multicolumn{4}{c|}{0010000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & MFPCR rd,rs2 \\ +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1101011} & +\multicolumn{4}{c|}{0010000001} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & MTPCR rs1,rs2 \\ +\cline{2-9} + + +& +\multicolumn{1}{|c|}{1101011} & +\multicolumn{4}{c|}{0100000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & ERET \\ +\cline{2-9} \end{tabular} @@ -11,18 +11,18 @@ unimp 31..0=0 j 31..25=0x60 imm25 jal 31..25=0x61 imm25 -lui 31..25=0x71 rd imm20 +jalr.c 31..25=0x62 24..22=0 rd rs1 imm12 +jalr.r 31..25=0x62 24..22=1 rd rs1 imm12 +jalr.j 31..25=0x62 24..22=2 rd rs1 imm12 -jalr.c 31..25=0x72 24..22=0 rd rs1 imm12 -jalr.r 31..25=0x72 24..22=1 rd rs1 imm12 -jalr.j 31..25=0x72 24..22=2 rd rs1 imm12 +beq 31..25=0x63 24..22=0 rs1 rs2 imm12lo imm12hi +bne 31..25=0x63 24..22=1 rs1 rs2 imm12lo imm12hi +blt 31..25=0x63 24..22=4 rs1 rs2 imm12lo imm12hi +bge 31..25=0x63 24..22=5 rs1 rs2 imm12lo imm12hi +bltu 31..25=0x63 24..22=6 rs1 rs2 imm12lo imm12hi +bgeu 31..25=0x63 24..22=7 rs1 rs2 imm12lo imm12hi -beq 31..25=0x73 24..22=0 rs1 rs2 imm12lo imm12hi -bne 31..25=0x73 24..22=1 rs1 rs2 imm12lo imm12hi -blt 31..25=0x73 24..22=4 rs1 rs2 imm12lo imm12hi -bge 31..25=0x73 24..22=5 rs1 rs2 imm12lo imm12hi -bltu 31..25=0x73 24..22=6 rs1 rs2 imm12lo imm12hi -bgeu 31..25=0x73 24..22=7 rs1 rs2 imm12lo imm12hi +lui 31..25=0x71 rd imm20 addi 31..25=0x74 24..22=0 rd rs1 imm12 slti 31..25=0x74 24..22=2 rd rs1 imm12 diff --git a/parse-opcodes b/parse-opcodes index 0a9965b..30273d8 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -24,23 +24,23 @@ arglut['shamt'] = (15,10) arglut['shamtw'] = (14,10) arglut['rm'] = (21,20) -typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw +typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,10=b typelut[0x00] = 0 typelut[0x60] = 1 typelut[0x61] = 1 +typelut[0x62] = 3 +typelut[0x63] = 10 typelut[0x71] = 2 -typelut[0x72] = 3 -typelut[0x73] = 3 typelut[0x74] = 3 typelut[0x75] = 4 typelut[0x76] = 3 typelut[0x77] = 4 typelut[0x78] = 3 -typelut[0x79] = 3 +typelut[0x79] = 10 typelut[0x7a] = 4 typelut[0x7b] = 4 typelut[0x68] = 3 -typelut[0x69] = 3 +typelut[0x69] = 10 typelut[0x6a] = 4 typelut[0x6b] = 4 typelut[0x6c] = 5 @@ -160,8 +160,8 @@ def str_inst(name,arguments): def print_unimp_type(name,match,arguments): print """ & -\\multicolumn{11}{|c|}{%s} & %s \\\\ -\\cline{2-12} +\\multicolumn{8}{|c|}{%s} & %s \\\\ +\\cline{2-9} """ % \ ( \ '0'*32, \ @@ -172,8 +172,8 @@ def print_j_type(name,match,arguments): print """ & \\multicolumn{1}{|c|}{%s} & -\\multicolumn{10}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\multicolumn{7}{c|}{%s} & %s \\\\ +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ @@ -184,91 +184,116 @@ def print_j_type(name,match,arguments): def print_lui_type(name,match,arguments): print """ & -\\multicolumn{2}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{8}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\multicolumn{1}{|c|}{%s} & +\\multicolumn{6}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ - str_arg('rd','',match,arguments), \ str_arg('imm20','',match,arguments), \ + str_arg('rd','',match,arguments), \ str_inst(name,arguments) \ ) -def print_i_type(name,match,arguments): +def print_b_type(name,match,arguments): print """ & -\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & +\\multicolumn{3}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & -\\multicolumn{5}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ - str_arg('rd','rs2',match,arguments), \ + binary(yank(match,22,3),3), \ + str_arg('imm12hi','',match,arguments), \ + str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ - binary(yank(match,12,3),3), \ + str_arg('imm12lo','',match,arguments), \ + str_inst(name,arguments) \ + ) + +def print_i_type(name,match,arguments): + print """ +& +\\multicolumn{1}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{4}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-9} + """ % \ + ( \ + binary(yank(match,25,7),7), \ + binary(yank(match,22,3),3), \ str_arg('imm12','',match,arguments), \ + str_arg('rs1','',match,arguments), \ + str_arg('rd','',match,arguments), \ str_inst(name,arguments) \ ) def print_ish_type(name,match,arguments): print """ & -\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{5}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ - str_arg('rd','',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,6,9),9), \ + binary(yank(match,22,3),3), \ + binary(yank(match,16,6),6), \ str_arg('shamt','',match,arguments), \ + str_arg('rs1','',match,arguments), \ + str_arg('rd','',match,arguments), \ str_inst(name,arguments) \ ) def print_ishw_type(name,match,arguments): print """ & -\\multicolumn{2}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{5}{c|}{%s} & +\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{0} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ + binary(yank(match,22,3),3), \ + binary(yank(match,16,6),6), \ + str_arg('shamtw','',match,arguments), \ str_arg('rd','',match,arguments), \ str_arg('rs1','',match,arguments), \ - binary(yank(match,6,9),9), \ - str_arg('shamtw','',match,arguments), \ str_inst(name,arguments) \ ) def print_r_type(name,match,arguments): print """ & -\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{|c|}{%s} & +\\multicolumn{4}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{6}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ + binary(yank(match,15,10),10), \ str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ - binary(yank(match,5,10),10), \ str_arg('rd','',match,arguments), \ str_inst(name,arguments) \ ) @@ -276,22 +301,22 @@ def print_r_type(name,match,arguments): def print_r_rm_type(name,match,arguments): print """ & -\\multicolumn{2}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{2}{c|}{%s} & -\\multicolumn{3}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ + binary(yank(match,22,3),3), \ + str_arg('rm','',match,arguments), \ + binary(yank(match,15,5),5), \ str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ - binary(yank(match,13,2),2), \ - str_arg('rm','',match,arguments), \ - binary(yank(match,5,6),6), \ str_arg('rd','',match,arguments), \ str_inst(name,arguments) \ ) @@ -299,20 +324,20 @@ def print_r_rm_type(name,match,arguments): def print_r4_type(name,match,arguments): print """ & -\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{|c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{4}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ + binary(yank(match,20,5),5), \ + str_arg('rs3','',match,arguments), \ str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ - binary(yank(match,10,5),5), \ - str_arg('rs3','',match,arguments), \ str_arg('rd','',match,arguments), \ str_inst(name,arguments) \ ) @@ -320,24 +345,22 @@ def print_r4_type(name,match,arguments): def print_r4_rm_type(name,match,arguments): print """ & -\\multicolumn{2}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-12} +\\cline{2-9} """ % \ ( \ binary(yank(match,25,7),7), \ - str_arg('rs2','',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,13,2),2), \ + binary(yank(match,22,3),3), \ str_arg('rm','',match,arguments), \ - binary(yank(match,10,1),1), \ str_arg('rs3','',match,arguments), \ + str_arg('rs2','',match,arguments), \ + str_arg('rs1','',match,arguments), \ str_arg('rd','',match,arguments), \ str_inst(name,arguments) \ ) @@ -363,56 +386,54 @@ def print_header(): \\hspace*{0.1in} & \\hspace*{0.5in} \\\\ & -\\instbitrange{31}{27} & -\\instbitrange{26}{25} & -\\instbitrange{24}{20} & -\\instbitrange{19}{15} & -\\instbitrange{14}{13} & -\\instbit{12} & -\\instbit{11} & -\\instbit{10} & -\\instbitrange{9}{6} & -\\instbit{5} & +\\instbitrange{31}{25} & +\\instbitrange{24}{22} & +\\instbitrange{21}{20} & +\\instbitrange{19}{16} & +\\instbit{15} & +\\instbitrange{14}{10} & +\\instbitrange{9}{5} & \\instbitrange{4}{0} \\\\ -\\cline{2-12} +\\cline{2-9} & -\\multicolumn{1}{|c|}{opcode5} & -\\multicolumn{10}{c|}{jump target} & J-type \\\\ -\\cline{2-12} +\\multicolumn{1}{|c|}{opcode} & +\\multicolumn{7}{c|}{jump target} & J-type \\\\ +\\cline{2-9} & -\\multicolumn{2}{|c|}{opcode} & -\\multicolumn{1}{c|}{rd} & -\\multicolumn{8}{c|}{LUI-immediate} & LUI-type \\\\ -\\cline{2-12} +\\multicolumn{1}{|c|}{opcode} & +\\multicolumn{6}{c|}{LUI-immediate} & +\\multicolumn{1}{c|}{rd} & LUI-type \\\\ +\\cline{2-9} & -\\multicolumn{2}{|c|}{opcode} & -\\multicolumn{1}{c|}{rd/rs2} & +\\multicolumn{1}{|c|}{opcode} & +\\multicolumn{1}{c|}{funct3} & +\\multicolumn{4}{c|}{immediate} & \\multicolumn{1}{c|}{rs1} & -\\multicolumn{2}{c|}{funct3} & -\\multicolumn{5}{c|}{immediate} & I-type \\\\ -\\cline{2-12} +\\multicolumn{1}{c|}{rd} & I-type \\\\ +\\cline{2-9} & -\\multicolumn{2}{|c|}{opcode} & -\\multicolumn{1}{c|}{rd} & +\\multicolumn{1}{|c|}{opcode} & +\\multicolumn{1}{c|}{funct3} & +\\multicolumn{3}{c|}{immed[11:5]} & +\\multicolumn{1}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & -\\multicolumn{5}{c|}{funct9} & -\\multicolumn{2}{c|}{shamt} & ISH-type \\\\ -\\cline{2-12} +\\multicolumn{1}{c|}{immed[4:0]} & B-type \\\\ +\\cline{2-9} & -\\multicolumn{2}{|c|}{opcode} & +\\multicolumn{1}{|c|}{opcode} & +\\multicolumn{4}{c|}{funct10} & \\multicolumn{1}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & -\\multicolumn{6}{c|}{funct10} & \\multicolumn{1}{c|}{rd} & R-type \\\\ -\\cline{2-12} +\\cline{2-9} & -\\multicolumn{2}{|c|}{opcode} & +\\multicolumn{1}{|c|}{opcode} & +\\multicolumn{2}{c|}{funct5} & +\\multicolumn{2}{c|}{rs3} & \\multicolumn{1}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & -\\multicolumn{4}{c|}{funct5} & -\\multicolumn{2}{c|}{rs3} & \\multicolumn{1}{c|}{rd} & R4-type \\\\ -\\cline{2-12} +\\cline{2-9} """ def print_subtitle(title): @@ -421,7 +442,7 @@ def print_subtitle(title): \\multicolumn{11}{c}{} & \\\\ & \\multicolumn{11}{c}{\\bf %s} & \\\\ -\\cline{2-12} +\\cline{2-9} """ % title def print_footer(caption): @@ -460,6 +481,8 @@ def print_insts(opcode,name,type,min,max): print_r4_rm_type(n,match[n],arguments[n]) elif types[n] == 9: print_r_rm_type(n,match[n],arguments[n]) + elif types[n] == 10: + print_b_type(n,match[n],arguments[n]) def make_latex_table(): print_header() @@ -467,9 +490,9 @@ def make_latex_table(): print_insts(0x00,'',-1,-1,-1) print_subtitle('Control Transfer Instructions') print_insts(0x60,'',-1,-1,-1) - print_insts(0x64,'',-1,-1,-1) - print_insts(0x7b,'',-1,0x000,0x002) - print_insts(0x73,'',-1,-1,-1) + print_insts(0x61,'',-1,-1,-1) + print_insts(0x62,'',-1,-1,-1) + print_insts(0x63,'',-1,-1,-1) print_subtitle('Memory Instructions') print_insts(0x78,'',-1,-1,-1) print_insts(0x79,'',-1,-1,-1) @@ -583,9 +606,9 @@ def make_latex_table(): print_insts(-1,'c.lt.d',-1,-1,-1) print_insts(-1,'c.le.d',-1,-1,-1) print_subtitle('Miscellaneous Instructions') - print_insts(0x7b,'',-1,0x080,0x300) + print_insts(0x7b,'',-1,-1,-1) print_subtitle('Privileged Instructions') - print_insts(0x7e,'',-1,-1,-1) + print_insts(0x6b,'',-1,-1,-1) print_footer(1) def str_verilog_arg(arg0,arg1,match,arguments): @@ -618,8 +641,20 @@ def print_verilog_lui_type(name,match,arguments): ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('imm20','',match,arguments) \ + str_verilog_arg('imm20','',match,arguments), \ + str_verilog_arg('rd','',match,arguments) \ + ) + +def print_verilog_b_type(name,match,arguments): + print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + binary(yank(match,22,3),3), \ + str_verilog_arg('imm12hi','',match,arguments), \ + str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rs1','',match,arguments), \ + str_verilog_arg('imm12lo','',match,arguments) \ ) def print_verilog_i_type(name,match,arguments): @@ -627,57 +662,59 @@ def print_verilog_i_type(name,match,arguments): ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ - str_verilog_arg('rd','rs2',match,arguments), \ + binary(yank(match,22,3),3), \ + str_verilog_arg('imm12','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,12,3),3), \ - str_verilog_arg('imm12','',match,arguments) \ + str_verilog_arg('rd','',match,arguments) \ ) def print_verilog_ish_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ + print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ - str_verilog_arg('rd','',match,arguments), \ + binary(yank(match,22,3),3), \ + binary(yank(match,16,6),6), \ + str_verilog_arg('shamt','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,6,9),9), \ - str_verilog_arg('shamt','',match,arguments) \ + str_verilog_arg('rd','',match,arguments) \ ) def print_verilog_ishw_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_0_%s" % \ + print "`define %-10s 32'b%s_%s_%s_0_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ - str_verilog_arg('rd','',match,arguments), \ + binary(yank(match,22,3),3), \ + binary(yank(match,16,6),6), \ + str_verilog_arg('shamtw','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,6,9),9), \ - str_verilog_arg('shamtw','',match,arguments) \ + str_verilog_arg('rd','',match,arguments) \ ) def print_verilog_r4_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \ + print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ + binary(yank(match,22,3),3), \ + binary(yank(match,20,2),2), \ + str_verilog_arg('rs3','',match,arguments), \ str_verilog_arg('rs2','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,10,5),5), \ - str_verilog_arg('rs3','',match,arguments), \ str_verilog_arg('rd','',match,arguments) \ ) def print_verilog_r4_rm_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s_%s" % \ + print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ - str_verilog_arg('rs2','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,13,2),2), \ + binary(yank(match,22,3),3), \ str_verilog_arg('rm','',match,arguments), \ - binary(yank(match,10,1),1), \ str_verilog_arg('rs3','',match,arguments), \ + str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rs1','',match,arguments), \ str_verilog_arg('rd','',match,arguments) \ ) @@ -686,11 +723,11 @@ def print_verilog_r_rm_type(name,match,arguments): ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ + binary(yank(match,22,3),3), \ + str_verilog_arg('rm','',match,arguments), \ + binary(yank(match,15,5),5), \ str_verilog_arg('rs2','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,13,2),2), \ - str_verilog_arg('rm','',match,arguments), \ - binary(yank(match,5,6),6), \ str_verilog_arg('rd','',match,arguments) \ ) @@ -699,9 +736,9 @@ def print_verilog_r_type(name,match,arguments): ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ + binary(yank(match,15,10),10), \ str_verilog_arg('rs2','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,5,10),10), \ str_verilog_arg('rd','',match,arguments) \ ) @@ -727,6 +764,8 @@ def make_verilog(): print_verilog_r4_rm_type(name,match[name],arguments[name]) elif types[name] == 9: print_verilog_r_rm_type(name,match[name],arguments[name]) + elif types[name] == 10: + print_verilog_b_type(name,match[name],arguments[name]) for line in sys.stdin: line = line.partition('#') |