diff options
| author |  Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-31 18:13:54 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-31 18:13:54 -0800 |
| commit | 92b7ccecbf4ef36feaeaabc656fb0eb040fc7885 (patch) | |
| tree | 8a2b1b0eacd47f35640e4a4a2a8f6c6343dd6886 | |
| parent | 4159b9b3fdbebf7f3000acec57257812663834d9 (diff) | |
[opcodes] fixed verilog generation for shifts
| -rw-r--r-- | inst.v | 12 | ||||
| -rwxr-xr-x | parse-opcodes | 6 |
2 files changed, 9 insertions, 9 deletions
@@ -12,12 +12,12 @@ `define BGEU 32'b?????_?????_?????_???????_111_1100011 `define LUI 32'b?????_????????????????????_0110111 `define ADDI 32'b?????_?????_????????????_000_0010011 -`define SLLI 32'b?????_?????_??????_000000_001_0010011 +`define SLLI 32'b?????_?????_000000_??????_001_0010011 `define SLTI 32'b?????_?????_????????????_010_0010011 `define SLTIU 32'b?????_?????_????????????_011_0010011 `define XORI 32'b?????_?????_????????????_100_0010011 -`define SRLI 32'b?????_?????_??????_000000_101_0010011 -`define SRAI 32'b?????_?????_??????_000000_101_0010011 +`define SRLI 32'b?????_?????_000000_??????_101_0010011 +`define SRAI 32'b?????_?????_000001_??????_101_0010011 `define ORI 32'b?????_?????_????????????_110_0010011 `define ANDI 32'b?????_?????_????????????_111_0010011 `define ADD 32'b?????_?????_?????_0000000000_0110011 @@ -39,9 +39,9 @@ `define REM 32'b?????_?????_?????_0000001110_0110011 `define REMU 32'b?????_?????_?????_0000001111_0110011 `define ADDIW 32'b?????_?????_????????????_000_0011011 -`define SLLIW 32'b?????_?????_0_?????_000000_001_0011011 -`define SRLIW 32'b?????_?????_0_?????_000000_101_0011011 -`define SRAIW 32'b?????_?????_0_?????_000000_101_0011011 +`define SLLIW 32'b?????_?????_000000_0_?????_001_0011011 +`define SRLIW 32'b?????_?????_000000_0_?????_101_0011011 +`define SRAIW 32'b?????_?????_000001_0_?????_101_0011011 `define ADDW 32'b?????_?????_?????_0000000000_0111011 `define SUBW 32'b?????_?????_?????_1000000000_0111011 `define SLLW 32'b?????_?????_?????_0000000001_0111011 diff --git a/parse-opcodes b/parse-opcodes index 911c60e..3f9f958 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -649,20 +649,20 @@ def print_verilog_ish_type(name,match,arguments): name.replace('.','_').upper(), \ str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ + binary(yank(match,16,6),6), \ str_verilog_arg('shamt','',match,arguments), \ - binary(yank(match,10,6),6), \ binary(yank(match,7,3),3), \ binary(yank(match,0,7),7) \ ) def print_verilog_ishw_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_0_%s_%s_%s_%s" % \ + print "`define %-10s 32'b%s_%s_%s_0_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ + binary(yank(match,16,6),6), \ str_verilog_arg('shamtw','',match,arguments), \ - binary(yank(match,10,6),6), \ binary(yank(match,7,3),3), \ binary(yank(match,0,7),7) \ ) |