[opcodes, pk, sim, xcc] made jumps shorter and PC-relative

4 files changed, 12 insertions, 18 deletions

diff --git a/inst.v b/inst.v
index ed0bd15..2702523 100644
--- a/inst.v
+++ b/inst.v
@@ -1,6 +1,6 @@
 `define UNIMP      32'b00000000000000000000000000000000
-`define J          32'b11000_???????????????????????????
-`define JAL        32'b11001_???????????????????????????
+`define J          32'b1100000_?????????????????????????
+`define JAL        32'b1100001_?????????????????????????
 `define LUI        32'b1110001_?????_????????????????????
 `define BEQ        32'b1110011_?????_?????_000_????????????
 `define BNE        32'b1110011_?????_?????_001_????????????
diff --git a/instr-table.tex b/instr-table.tex
index 9d49b40..56f5c2a 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -90,14 +90,8 @@
   
 
 &
-\multicolumn{1}{|c|}{11000} &
-\multicolumn{10}{c|}{imm27} & J imm27 \\
-\cline{2-12}
-  
-
-&
-\multicolumn{1}{|c|}{11001} &
-\multicolumn{10}{c|}{imm27} & JAL imm27 \\
+\multicolumn{1}{|c|}{1100000} &
+\multicolumn{10}{c|}{imm25} & J imm25 \\
 \cline{2-12}
   
 
diff --git a/opcodes b/opcodes
index 325264f..a585d97 100644
--- a/opcodes
+++ b/opcodes
@@ -8,8 +8,8 @@
 
 unimp   31..0=0
 
-j       31..27=0x18 imm27 # opcodes 0x60-0x64
-jal     31..27=0x19 imm27 # opcodes 0x64-0x68
+j       31..25=0x60 imm25
+jal     31..25=0x61 imm25
 
 lui     31..25=0x71 rdi imm20
 
diff --git a/parse-opcodes b/parse-opcodes
index 50e602c..b1860df 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -16,7 +16,7 @@ arglut['rs2'] = (24,20)
 arglut['rs1'] = (19,15)
 arglut['rdr'] = (4,0)
 arglut['rs3'] = (9,5)
-arglut['imm27'] = (26,0)
+arglut['imm25'] = (24,0)
 arglut['imm20'] = (19,0)
 arglut['imm12'] = (11,0)
 arglut['shamt'] = (5,0)
@@ -26,7 +26,7 @@ arglut['rm'] = (12,11)
 typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw
 typelut[0x00] = 0
 typelut[0x60] = 1
-typelut[0x64] = 1
+typelut[0x61] = 1
 typelut[0x71] = 2
 typelut[0x73] = 3
 typelut[0x74] = 3
@@ -174,8 +174,8 @@ def print_j_type(name,match,arguments):
 \\cline{2-12}
   """ % \
   ( \
-    binary(yank(match,27,5),5), \
-    str_arg('imm27','',match,arguments), \
+    binary(yank(match,25,7),7), \
+    str_arg('imm25','',match,arguments), \
     str_inst(name,arguments) \
   )
 
@@ -607,8 +607,8 @@ def print_verilog_j_type(name,match,arguments):
   print "`define %-10s 32'b%s_%s" % \
   ( \
     name.replace('.','_').upper(), \
-    binary(yank(match,27,5),5), \
-    str_verilog_arg('imm27','',match,arguments) \
+    binary(yank(match,25,7),7), \
+    str_verilog_arg('imm25','',match,arguments) \
   )
 
 def print_verilog_lui_type(name,match,arguments):