diff options
| author |  Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-01-03 19:12:24 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-01-03 19:13:39 -0800 |
| commit | 46ae58e4ae587d7cafca539888f917d27f948ffb (patch) | |
| tree | 56e6afff97f258cea9c277fc99d6f5874304a53c | |
| parent | 5cab356399c5b7358de571a79aa2aaf060c8a5f4 (diff) | |
[opcodes,pk,sim,xcc] flip fields to favor little endian
| -rw-r--r-- | inst.v | 304 | ||||
| -rw-r--r-- | instr-table.tex | 1673 | ||||
| -rw-r--r-- | opcodes | 362 | ||||
| -rwxr-xr-x | parse-opcodes | 118 |
4 files changed, 1508 insertions, 949 deletions
@@ -1,153 +1,153 @@ `define UNIMP 32'b00000000000000000000000000000000 -`define J 32'b1100000_????????????????????????? -`define JAL 32'b1100001_????????????????????????? -`define JALR_C 32'b1100010_000_????????????_?????_????? -`define JALR_R 32'b1100010_001_????????????_?????_????? -`define JALR_J 32'b1100010_010_????????????_?????_????? -`define BEQ 32'b1100011_000_???????_?????_?????_????? -`define BNE 32'b1100011_001_???????_?????_?????_????? -`define BLT 32'b1100011_100_???????_?????_?????_????? -`define BGE 32'b1100011_101_???????_?????_?????_????? -`define BLTU 32'b1100011_110_???????_?????_?????_????? -`define BGEU 32'b1100011_111_???????_?????_?????_????? -`define LUI 32'b1110001_????????????????????_????? -`define ADDI 32'b1110100_000_????????????_?????_????? -`define SLTI 32'b1110100_010_????????????_?????_????? -`define SLTIU 32'b1110100_011_????????????_?????_????? -`define ANDI 32'b1110100_100_????????????_?????_????? -`define ORI 32'b1110100_101_????????????_?????_????? -`define XORI 32'b1110100_110_????????????_?????_????? -`define SLLI 32'b1110100_111_000001_??????_?????_????? -`define SRLI 32'b1110100_111_000010_??????_?????_????? -`define SRAI 32'b1110100_111_000011_??????_?????_????? -`define ADD 32'b1110101_0000000000_?????_?????_????? -`define SUB 32'b1110101_0000000001_?????_?????_????? -`define SLT 32'b1110101_0000000010_?????_?????_????? -`define SLTU 32'b1110101_0000000011_?????_?????_????? -`define AND 32'b1110101_0000000100_?????_?????_????? -`define OR 32'b1110101_0000000101_?????_?????_????? -`define XOR 32'b1110101_0000000110_?????_?????_????? -`define NOR 32'b1110101_0000000111_?????_?????_????? -`define SLL 32'b1110101_1110000010_?????_?????_????? -`define SRL 32'b1110101_1110000100_?????_?????_????? -`define SRA 32'b1110101_1110000110_?????_?????_????? -`define MUL 32'b1110101_0010000000_?????_?????_????? -`define MULH 32'b1110101_0010000010_?????_?????_????? -`define MULHU 32'b1110101_0010000011_?????_?????_????? -`define DIV 32'b1110101_0010000100_?????_?????_????? -`define DIVU 32'b1110101_0010000101_?????_?????_????? -`define REM 32'b1110101_0010000110_?????_?????_????? -`define REMU 32'b1110101_0010000111_?????_?????_????? -`define ADDIW 32'b1110110_000_????????????_?????_????? -`define SLLIW 32'b1110110_111_000001_0_?????_?????_????? -`define SRLIW 32'b1110110_111_000010_0_?????_?????_????? -`define SRAIW 32'b1110110_111_000011_0_?????_?????_????? -`define ADDW 32'b1110111_0000000000_?????_?????_????? -`define SUBW 32'b1110111_0000000001_?????_?????_????? -`define SLLW 32'b1110111_1110000010_?????_?????_????? -`define SRLW 32'b1110111_1110000100_?????_?????_????? -`define SRAW 32'b1110111_1110000110_?????_?????_????? -`define MULW 32'b1110111_0010000000_?????_?????_????? -`define MULHW 32'b1110111_0010000010_?????_?????_????? -`define MULHUW 32'b1110111_0010000011_?????_?????_????? -`define DIVW 32'b1110111_0010000100_?????_?????_????? -`define DIVUW 32'b1110111_0010000101_?????_?????_????? -`define REMW 32'b1110111_0010000110_?????_?????_????? -`define REMUW 32'b1110111_0010000111_?????_?????_????? -`define LB 32'b1111000_000_????????????_?????_????? -`define LH 32'b1111000_001_????????????_?????_????? -`define LW 32'b1111000_010_????????????_?????_????? -`define LD 32'b1111000_011_????????????_?????_????? -`define LBU 32'b1111000_100_????????????_?????_????? -`define LHU 32'b1111000_101_????????????_?????_????? -`define LWU 32'b1111000_110_????????????_?????_????? -`define SYNCI 32'b1111000_111_????????????_?????_00000 -`define SB 32'b1111001_000_???????_?????_?????_????? -`define SH 32'b1111001_001_???????_?????_?????_????? -`define SW 32'b1111001_010_???????_?????_?????_????? -`define SD 32'b1111001_011_???????_?????_?????_????? -`define AMOW_ADD 32'b1111010_0100000000_?????_?????_????? -`define AMOW_SWAP 32'b1111010_0100000001_?????_?????_????? -`define AMOW_AND 32'b1111010_0100000010_?????_?????_????? -`define AMOW_OR 32'b1111010_0100000011_?????_?????_????? -`define AMOW_MIN 32'b1111010_0100000100_?????_?????_????? -`define AMOW_MAX 32'b1111010_0100000101_?????_?????_????? -`define AMOW_MINU 32'b1111010_0100000110_?????_?????_????? -`define AMOW_MAXU 32'b1111010_0100000111_?????_?????_????? -`define AMO_ADD 32'b1111010_0110000000_?????_?????_????? -`define AMO_SWAP 32'b1111010_0110000001_?????_?????_????? -`define AMO_AND 32'b1111010_0110000010_?????_?????_????? -`define AMO_OR 32'b1111010_0110000011_?????_?????_????? -`define AMO_MIN 32'b1111010_0110000100_?????_?????_????? -`define AMO_MAX 32'b1111010_0110000101_?????_?????_????? -`define AMO_MINU 32'b1111010_0110000110_?????_?????_????? -`define AMO_MAXU 32'b1111010_0110000111_?????_?????_????? -`define RDNPC 32'b1111011_0000000000_00000_00000_????? -`define MFCR 32'b1111011_0010000000_?????_00000_????? -`define MTCR 32'b1111011_0010000001_?????_?????_00000 -`define SYNC 32'b1111011_0100000000_00000_00000_00000 -`define SYSCALL 32'b1111011_011_????????????_00000_00000 -`define EI 32'b1101011_0000000000_00000_00000_????? -`define DI 32'b1101011_0000000001_00000_00000_????? -`define MFPCR 32'b1101011_0010000000_?????_00000_????? -`define MTPCR 32'b1101011_0010000001_?????_?????_00000 -`define ERET 32'b1101011_0100000000_00000_00000_00000 -`define ADD_S 32'b1101010_00_???_00000_?????_?????_????? -`define SUB_S 32'b1101010_00_???_00001_?????_?????_????? -`define MUL_S 32'b1101010_00_???_00010_?????_?????_????? -`define DIV_S 32'b1101010_00_???_00011_?????_?????_????? -`define SQRT_S 32'b1101010_00_???_00100_00000_?????_????? -`define SGNINJ_S 32'b1101010_0000000101_?????_?????_????? -`define SGNINJN_S 32'b1101010_0000000110_?????_?????_????? -`define SGNMUL_S 32'b1101010_0000000111_?????_?????_????? -`define ADD_D 32'b1101010_11_???_00000_?????_?????_????? -`define SUB_D 32'b1101010_11_???_00001_?????_?????_????? -`define MUL_D 32'b1101010_11_???_00010_?????_?????_????? -`define DIV_D 32'b1101010_11_???_00011_?????_?????_????? -`define SQRT_D 32'b1101010_11_???_00100_00000_?????_????? -`define SGNINJ_D 32'b1101010_1100000101_?????_?????_????? -`define SGNINJN_D 32'b1101010_1100000110_?????_?????_????? -`define SGNMUL_D 32'b1101010_1100000111_?????_?????_????? -`define CVT_L_S 32'b1101010_00_???_01000_00000_?????_????? -`define CVTU_L_S 32'b1101010_00_???_01001_00000_?????_????? -`define CVT_W_S 32'b1101010_00_???_01010_00000_?????_????? -`define CVTU_W_S 32'b1101010_00_???_01011_00000_?????_????? -`define CVT_L_D 32'b1101010_11_???_01000_00000_?????_????? -`define CVTU_L_D 32'b1101010_11_???_01001_00000_?????_????? -`define CVT_W_D 32'b1101010_11_???_01010_00000_?????_????? -`define CVTU_W_D 32'b1101010_11_???_01011_00000_?????_????? -`define CVT_S_L 32'b1101010_00_???_01100_00000_?????_????? -`define CVTU_S_L 32'b1101010_00_???_01101_00000_?????_????? -`define CVT_S_W 32'b1101010_00_???_01110_00000_?????_????? -`define CVTU_S_W 32'b1101010_00_???_01111_00000_?????_????? -`define CVT_D_L 32'b1101010_11_???_01100_00000_?????_????? -`define CVTU_D_L 32'b1101010_11_???_01101_00000_?????_????? -`define CVT_D_W 32'b1101010_1100001110_00000_?????_????? -`define CVTU_D_W 32'b1101010_1100001111_00000_?????_????? -`define CVT_S_D 32'b1101010_00_???_10011_00000_?????_????? -`define CVT_D_S 32'b1101010_1100010000_00000_?????_????? -`define C_EQ_S 32'b1101010_0000010101_?????_?????_????? -`define C_LT_S 32'b1101010_0000010110_?????_?????_????? -`define C_LE_S 32'b1101010_0000010111_?????_?????_????? -`define C_EQ_D 32'b1101010_1100010101_?????_?????_????? -`define C_LT_D 32'b1101010_1100010110_?????_?????_????? -`define C_LE_D 32'b1101010_1100010111_?????_?????_????? -`define MFF_S 32'b1101010_0001011000_?????_00000_????? -`define MFF_D 32'b1101010_1101011000_?????_00000_????? -`define MFFL_D 32'b1101010_1101011001_?????_00000_????? -`define MFFH_D 32'b1101010_1101011010_?????_00000_????? -`define MTF_S 32'b1101010_0001011100_00000_?????_????? -`define MTF_D 32'b1101010_1101011100_00000_?????_????? -`define MTFLH_D 32'b1101010_1101111100_?????_?????_????? -`define L_S 32'b1101000_010_????????????_?????_????? -`define L_D 32'b1101000_011_????????????_?????_????? -`define S_S 32'b1101001_010_???????_?????_?????_????? -`define S_D 32'b1101001_011_???????_?????_?????_????? -`define MADD_S 32'b1101100_00_???_?????_?????_?????_????? -`define MSUB_S 32'b1101101_00_???_?????_?????_?????_????? -`define NMSUB_S 32'b1101110_00_???_?????_?????_?????_????? -`define NMADD_S 32'b1101111_00_???_?????_?????_?????_????? -`define MADD_D 32'b1101100_11_???_?????_?????_?????_????? -`define MSUB_D 32'b1101101_11_???_?????_?????_?????_????? -`define NMSUB_D 32'b1101110_11_???_?????_?????_?????_????? -`define NMADD_D 32'b1101111_11_???_?????_?????_?????_????? +`define J 32'b?????????????????????????_1100000 +`define JAL 32'b?????????????????????????_1100001 +`define JALR_C 32'b?????_?????_????????????_000_1100010 +`define JALR_R 32'b?????_?????_????????????_001_1100010 +`define JALR_J 32'b?????_?????_????????????_010_1100010 +`define BEQ 32'b?????_?????_?????_???????_000_1100011 +`define BNE 32'b?????_?????_?????_???????_001_1100011 +`define BLT 32'b?????_?????_?????_???????_100_1100011 +`define BGE 32'b?????_?????_?????_???????_101_1100011 +`define BLTU 32'b?????_?????_?????_???????_110_1100011 +`define BGEU 32'b?????_?????_?????_???????_111_1100011 +`define LUI 32'b?????_????????????????????_1110001 +`define ADDI 32'b?????_?????_????????????_000_1110100 +`define SLTI 32'b?????_?????_????????????_010_1110100 +`define SLTIU 32'b?????_?????_????????????_011_1110100 +`define ANDI 32'b?????_?????_????????????_100_1110100 +`define ORI 32'b?????_?????_????????????_101_1110100 +`define XORI 32'b?????_?????_????????????_110_1110100 +`define SLLI 32'b?????_?????_??????_000001_111_1110100 +`define SRLI 32'b?????_?????_??????_000010_111_1110100 +`define SRAI 32'b?????_?????_??????_000011_111_1110100 +`define ADD 32'b?????_?????_?????_0000000000_1110101 +`define SUB 32'b?????_?????_?????_0000001000_1110101 +`define SLT 32'b?????_?????_?????_0000010000_1110101 +`define SLTU 32'b?????_?????_?????_0000011000_1110101 +`define AND 32'b?????_?????_?????_0000100000_1110101 +`define OR 32'b?????_?????_?????_0000101000_1110101 +`define XOR 32'b?????_?????_?????_0000110000_1110101 +`define NOR 32'b?????_?????_?????_0000111000_1110101 +`define SLL 32'b?????_?????_?????_0000001111_1110101 +`define SRL 32'b?????_?????_?????_0000010111_1110101 +`define SRA 32'b?????_?????_?????_0000011111_1110101 +`define MUL 32'b?????_?????_?????_0000000001_1110101 +`define MULH 32'b?????_?????_?????_0000010001_1110101 +`define MULHU 32'b?????_?????_?????_0000011001_1110101 +`define DIV 32'b?????_?????_?????_0000100001_1110101 +`define DIVU 32'b?????_?????_?????_0000101001_1110101 +`define REM 32'b?????_?????_?????_0000110001_1110101 +`define REMU 32'b?????_?????_?????_0000111001_1110101 +`define ADDIW 32'b?????_?????_????????????_000_1110110 +`define SLLIW 32'b?????_?????_0_?????_000001_111_1110110 +`define SRLIW 32'b?????_?????_0_?????_000010_111_1110110 +`define SRAIW 32'b?????_?????_0_?????_000011_111_1110110 +`define ADDW 32'b?????_?????_?????_0000000000_1110111 +`define SUBW 32'b?????_?????_?????_0000001000_1110111 +`define SLLW 32'b?????_?????_?????_0000001111_1110111 +`define SRLW 32'b?????_?????_?????_0000010111_1110111 +`define SRAW 32'b?????_?????_?????_0000011111_1110111 +`define MULW 32'b?????_?????_?????_0000000001_1110111 +`define MULHW 32'b?????_?????_?????_0000010001_1110111 +`define MULHUW 32'b?????_?????_?????_0000011001_1110111 +`define DIVW 32'b?????_?????_?????_0000100001_1110111 +`define DIVUW 32'b?????_?????_?????_0000101001_1110111 +`define REMW 32'b?????_?????_?????_0000110001_1110111 +`define REMUW 32'b?????_?????_?????_0000111001_1110111 +`define LB 32'b?????_?????_????????????_000_1111000 +`define LH 32'b?????_?????_????????????_001_1111000 +`define LW 32'b?????_?????_????????????_010_1111000 +`define LD 32'b?????_?????_????????????_011_1111000 +`define LBU 32'b?????_?????_????????????_100_1111000 +`define LHU 32'b?????_?????_????????????_101_1111000 +`define LWU 32'b?????_?????_????????????_110_1111000 +`define SYNCI 32'b00000_?????_????????????_111_1111000 +`define SB 32'b?????_?????_?????_???????_000_1111001 +`define SH 32'b?????_?????_?????_???????_001_1111001 +`define SW 32'b?????_?????_?????_???????_010_1111001 +`define SD 32'b?????_?????_?????_???????_011_1111001 +`define AMOW_ADD 32'b?????_?????_?????_0000000010_1111010 +`define AMOW_SWAP 32'b?????_?????_?????_0000001010_1111010 +`define AMOW_AND 32'b?????_?????_?????_0000010010_1111010 +`define AMOW_OR 32'b?????_?????_?????_0000011010_1111010 +`define AMOW_MIN 32'b?????_?????_?????_0000100010_1111010 +`define AMOW_MAX 32'b?????_?????_?????_0000101010_1111010 +`define AMOW_MINU 32'b?????_?????_?????_0000110010_1111010 +`define AMOW_MAXU 32'b?????_?????_?????_0000111010_1111010 +`define AMO_ADD 32'b?????_?????_?????_0000000011_1111010 +`define AMO_SWAP 32'b?????_?????_?????_0000001011_1111010 +`define AMO_AND 32'b?????_?????_?????_0000010011_1111010 +`define AMO_OR 32'b?????_?????_?????_0000011011_1111010 +`define AMO_MIN 32'b?????_?????_?????_0000100011_1111010 +`define AMO_MAX 32'b?????_?????_?????_0000101011_1111010 +`define AMO_MINU 32'b?????_?????_?????_0000110011_1111010 +`define AMO_MAXU 32'b?????_?????_?????_0000111011_1111010 +`define RDNPC 32'b?????_00000_00000_0000000000_1111011 +`define MFCR 32'b?????_00000_?????_0000000001_1111011 +`define MTCR 32'b00000_?????_?????_0000001001_1111011 +`define SYNC 32'b00000_00000_00000_0000000010_1111011 +`define SYSCALL 32'b00000_00000_????????????_011_1111011 +`define EI 32'b?????_00000_00000_0000000000_1101011 +`define DI 32'b?????_00000_00000_0000001000_1101011 +`define MFPCR 32'b?????_00000_?????_0000000001_1101011 +`define MTPCR 32'b00000_?????_?????_0000001001_1101011 +`define ERET 32'b00000_00000_00000_0000000010_1101011 +`define ADD_S 32'b?????_?????_?????_00000_???_00_1101010 +`define SUB_S 32'b?????_?????_?????_00001_???_00_1101010 +`define MUL_S 32'b?????_?????_?????_00010_???_00_1101010 +`define DIV_S 32'b?????_?????_?????_00011_???_00_1101010 +`define SQRT_S 32'b?????_?????_00000_00100_???_00_1101010 +`define SGNINJ_S 32'b?????_?????_?????_0010100000_1101010 +`define SGNINJN_S 32'b?????_?????_?????_0011000000_1101010 +`define SGNMUL_S 32'b?????_?????_?????_0011100000_1101010 +`define ADD_D 32'b?????_?????_?????_00000_???_11_1101010 +`define SUB_D 32'b?????_?????_?????_00001_???_11_1101010 +`define MUL_D 32'b?????_?????_?????_00010_???_11_1101010 +`define DIV_D 32'b?????_?????_?????_00011_???_11_1101010 +`define SQRT_D 32'b?????_?????_00000_00100_???_11_1101010 +`define SGNINJ_D 32'b?????_?????_?????_0010100011_1101010 +`define SGNINJN_D 32'b?????_?????_?????_0011000011_1101010 +`define SGNMUL_D 32'b?????_?????_?????_0011100011_1101010 +`define CVT_L_S 32'b?????_?????_00000_01000_???_00_1101010 +`define CVTU_L_S 32'b?????_?????_00000_01001_???_00_1101010 +`define CVT_W_S 32'b?????_?????_00000_01010_???_00_1101010 +`define CVTU_W_S 32'b?????_?????_00000_01011_???_00_1101010 +`define CVT_L_D 32'b?????_?????_00000_01000_???_11_1101010 +`define CVTU_L_D 32'b?????_?????_00000_01001_???_11_1101010 +`define CVT_W_D 32'b?????_?????_00000_01010_???_11_1101010 +`define CVTU_W_D 32'b?????_?????_00000_01011_???_11_1101010 +`define CVT_S_L 32'b?????_?????_00000_01100_???_00_1101010 +`define CVTU_S_L 32'b?????_?????_00000_01101_???_00_1101010 +`define CVT_S_W 32'b?????_?????_00000_01110_???_00_1101010 +`define CVTU_S_W 32'b?????_?????_00000_01111_???_00_1101010 +`define CVT_D_L 32'b?????_?????_00000_01100_???_11_1101010 +`define CVTU_D_L 32'b?????_?????_00000_01101_???_11_1101010 +`define CVT_D_W 32'b?????_?????_00000_0111000011_1101010 +`define CVTU_D_W 32'b?????_?????_00000_0111100011_1101010 +`define CVT_S_D 32'b?????_?????_00000_10011_???_00_1101010 +`define CVT_D_S 32'b?????_?????_00000_1000000011_1101010 +`define C_EQ_S 32'b?????_?????_?????_1010100000_1101010 +`define C_LT_S 32'b?????_?????_?????_1011000000_1101010 +`define C_LE_S 32'b?????_?????_?????_1011100000_1101010 +`define C_EQ_D 32'b?????_?????_?????_1010100011_1101010 +`define C_LT_D 32'b?????_?????_?????_1011000011_1101010 +`define C_LE_D 32'b?????_?????_?????_1011100011_1101010 +`define MFF_S 32'b?????_00000_?????_1100001000_1101010 +`define MFF_D 32'b?????_00000_?????_1100001011_1101010 +`define MFFL_D 32'b?????_00000_?????_1100101011_1101010 +`define MFFH_D 32'b?????_00000_?????_1101001011_1101010 +`define MTF_S 32'b?????_?????_00000_1110001000_1101010 +`define MTF_D 32'b?????_?????_00000_1110001011_1101010 +`define MTFLH_D 32'b?????_?????_?????_1110001111_1101010 +`define L_S 32'b?????_?????_????????????_010_1101000 +`define L_D 32'b?????_?????_????????????_011_1101000 +`define S_S 32'b?????_?????_?????_???????_010_1101001 +`define S_D 32'b?????_?????_?????_???????_011_1101001 +`define MADD_S 32'b?????_?????_?????_?????_???_00_1101100 +`define MSUB_S 32'b?????_?????_?????_?????_???_00_1101101 +`define NMSUB_S 32'b?????_?????_?????_?????_???_00_1101110 +`define NMADD_S 32'b?????_?????_?????_?????_???_00_1101111 +`define MADD_D 32'b?????_?????_?????_?????_???_11_1101100 +`define MSUB_D 32'b?????_?????_?????_?????_???_11_1101101 +`define NMSUB_D 32'b?????_?????_?????_?????_???_11_1101110 +`define NMADD_D 32'b?????_?????_?????_?????_???_11_1101111 diff --git a/instr-table.tex b/instr-table.tex index e2c4f49..d35d345 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -80,26 +80,19 @@ & -\multicolumn{9}{c}{} & \\ -& -\multicolumn{9}{c}{\bf Control Transfer Instructions} & \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1100000} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{8}{c|}{imm25} & J imm25 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1100001} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{8}{c|}{imm25} & JAL imm25 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1100010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & @@ -108,8 +101,8 @@ & -\multicolumn{1}{|c|}{1100010} & -\multicolumn{2}{c|}{001} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & JALR.R rd,rs1,imm12 \\ @@ -117,8 +110,8 @@ & -\multicolumn{1}{|c|}{1100010} & -\multicolumn{2}{c|}{010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & JALR.J rd,rs1,imm12 \\ @@ -126,74 +119,470 @@ & -\multicolumn{1}{|c|}{1100011} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & BEQ rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & BEQ imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1100011} & -\multicolumn{2}{c|}{001} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & BNE rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & BNE imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1100011} & -\multicolumn{2}{c|}{100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & BLT rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & BLT imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1100011} & -\multicolumn{2}{c|}{101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & BGE rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & BGE imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1100011} & -\multicolumn{2}{c|}{110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & BLTU rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & BLTU imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1100011} & -\multicolumn{2}{c|}{111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & BGEU rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & BGEU imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{9}{c}{} & \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{7}{c|}{imm20} & +\multicolumn{1}{c|}{rd} & LUI rd,imm20 \\ +\cline{2-10} + + & -\multicolumn{9}{c}{\bf Memory Instructions} & \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & ADDI rd,rs1,imm12 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SLTI rd,rs1,imm12 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SLTIU rd,rs1,imm12 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & ANDI rd,rs1,imm12 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & ORI rd,rs1,imm12 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & XORI rd,rs1,imm12 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{2}{c|}{000000} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SLLI rd,rs1,shamt \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{2}{c|}{000000} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SRLI rd,rs1,shamt \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{2}{c|}{000000} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SRAI rd,rs1,shamt \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & ADD rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SUB rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SLT rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SLTU rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & AND rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & OR rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & XOR rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & NOR rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SLL rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SRL rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SRA rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MUL rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MULH rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MULHU rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & DIV rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & DIVU rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & REM rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & REMU rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & ADDIW rd,rs1,imm12 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{2}{c|}{000000} & +\multicolumn{1}{c|}{0} & +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rs1} & SLLIW rd,rs1,shamtw \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{2}{c|}{000000} & +\multicolumn{1}{c|}{0} & +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rs1} & SRLIW rd,rs1,shamtw \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{2}{c|}{000000} & +\multicolumn{1}{c|}{0} & +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rs1} & SRAIW rd,rs1,shamtw \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & ADDW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SUBW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SLLW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SRLW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SRAW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MULW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MULHW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MULHUW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & DIVW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & DIVUW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & REMW rd,rs1,rs2 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & REMUW rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1111000} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & @@ -202,8 +591,8 @@ & -\multicolumn{1}{|c|}{1111000} & -\multicolumn{2}{c|}{001} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & LH rd,rs1,imm12 \\ @@ -211,8 +600,8 @@ & -\multicolumn{1}{|c|}{1111000} & -\multicolumn{2}{c|}{010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & LW rd,rs1,imm12 \\ @@ -220,8 +609,8 @@ & -\multicolumn{1}{|c|}{1111000} & -\multicolumn{2}{c|}{011} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & LD rd,rs1,imm12 \\ @@ -229,8 +618,8 @@ & -\multicolumn{1}{|c|}{1111000} & -\multicolumn{2}{c|}{100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & LBU rd,rs1,imm12 \\ @@ -238,8 +627,8 @@ & -\multicolumn{1}{|c|}{1111000} & -\multicolumn{2}{c|}{101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & LHU rd,rs1,imm12 \\ @@ -247,8 +636,8 @@ & -\multicolumn{1}{|c|}{1111000} & -\multicolumn{2}{c|}{110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & LWU rd,rs1,imm12 \\ @@ -256,8 +645,8 @@ & -\multicolumn{1}{|c|}{1111000} & -\multicolumn{2}{c|}{111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & SYNCI rs1,imm12 \\ @@ -265,55 +654,48 @@ & -\multicolumn{1}{|c|}{1111001} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & SB rs2,rs1,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & SB imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1111001} & -\multicolumn{2}{c|}{001} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & SH rs2,rs1,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & SH imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1111001} & -\multicolumn{2}{c|}{010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & SW rs2,rs1,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & SW imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1111001} & -\multicolumn{2}{c|}{011} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & SD rs2,rs1,imm12 \\ +\multicolumn{1}{c|}{imm12lo} & SD imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{9}{c}{} & \\ -& -\multicolumn{9}{c}{\bf Atomic Memory Instructions} & \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0100000000} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOW.ADD rd,rs1,rs2 \\ @@ -321,8 +703,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0100000001} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOW.SWAP rd,rs1,rs2 \\ @@ -330,8 +712,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0100000010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOW.AND rd,rs1,rs2 \\ @@ -339,8 +721,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0100000011} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOW.OR rd,rs1,rs2 \\ @@ -348,8 +730,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0100000100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOW.MIN rd,rs1,rs2 \\ @@ -357,8 +739,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0100000101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOW.MAX rd,rs1,rs2 \\ @@ -366,8 +748,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0100000110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOW.MINU rd,rs1,rs2 \\ @@ -375,8 +757,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0100000111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOW.MAXU rd,rs1,rs2 \\ @@ -384,8 +766,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0110000000} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMO.ADD rd,rs1,rs2 \\ @@ -393,8 +775,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0110000001} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMO.SWAP rd,rs1,rs2 \\ @@ -402,8 +784,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0110000010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMO.AND rd,rs1,rs2 \\ @@ -411,8 +793,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0110000011} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMO.OR rd,rs1,rs2 \\ @@ -420,8 +802,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0110000100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMO.MIN rd,rs1,rs2 \\ @@ -429,8 +811,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0110000101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMO.MAX rd,rs1,rs2 \\ @@ -438,8 +820,8 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0110000110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMO.MINU rd,rs1,rs2 \\ @@ -447,504 +829,721 @@ & -\multicolumn{1}{|c|}{1111010} & -\multicolumn{5}{c|}{0110000111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMO.MAXU rd,rs1,rs2 \\ \cline{2-10} -\end{tabular} -\end{center} -\end{small} +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & RDNPC rd \\ +\cline{2-10} + -\label{instr-table} -\end{table} +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & MFCR rd,rs2 \\ +\cline{2-10} -\newpage +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & MTCR rs1,rs2 \\ +\cline{2-10} + -\begin{table}[p] -\begin{small} -\begin{center} -\begin{tabular}{rcccccccccl} - & -\hspace*{0.6in} & -\hspace*{0.3in} & -\hspace*{0.1in} & -\hspace*{0.2in} & -\hspace*{0.2in} & -\hspace*{0.1in} & -\hspace*{0.3in} & -\hspace*{0.3in} & -\hspace*{0.3in} \\ - & -\instbitrange{31}{25} & -\instbitrange{24}{23} & -\instbit{22} & -\instbitrange{21}{20} & -\instbitrange{19}{16} & -\instbit{15} & -\instbitrange{14}{10} & -\instbitrange{9}{5} & -\instbitrange{4}{0} \\ +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & SYNC \\ \cline{2-10} + + & -\multicolumn{1}{|c|}{opcode} & -\multicolumn{8}{c|}{jump target} & J-type \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & SYSCALL imm12 \\ \cline{2-10} + + & -\multicolumn{1}{|c|}{opcode} & -\multicolumn{7}{c|}{LUI-immediate} & -\multicolumn{1}{c|}{rd} & LUI-type \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & EI rd \\ \cline{2-10} + + & -\multicolumn{1}{|c|}{opcode} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{4}{c|}{immediate} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & I-type \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & DI rd \\ \cline{2-10} + + & -\multicolumn{1}{|c|}{opcode} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{3}{c|}{immed[11:5]} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{immed[4:0]} & B-type \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & MFPCR rd,rs2 \\ \cline{2-10} + + & -\multicolumn{1}{|c|}{opcode} & -\multicolumn{5}{c|}{funct10} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & R-type \\ +\multicolumn{1}{c|}{00000} & MTPCR rs1,rs2 \\ \cline{2-10} + + & -\multicolumn{1}{|c|}{opcode} & -\multicolumn{3}{c|}{funct5} & -\multicolumn{2}{c|}{rs3} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & ERET \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & R4-type \\ +\multicolumn{1}{c|}{rd} & ADD.S rd,rs1,rs2[,rm] \\ \cline{2-10} & -\multicolumn{9}{c}{} & \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & SUB.S rd,rs1,rs2[,rm] \\ +\cline{2-10} + + & -\multicolumn{9}{c}{\bf Integer Compute Instructions} & \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MUL.S rd,rs1,rs2[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110001} & -\multicolumn{7}{c|}{imm20} & -\multicolumn{1}{c|}{rd} & LUI rd,imm20 \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & DIV.S rd,rs1,rs2[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{000} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & ADDI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SQRT.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{010} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLTI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SGNINJ.S rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{011} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLTIU rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SGNINJN.S rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{100} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & ANDI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SGNMUL.S rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{101} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & ORI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & ADD.D rd,rs1,rs2[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{110} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & XORI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SUB.D rd,rs1,rs2[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{111} & -\multicolumn{2}{c|}{000001} & -\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLLI rd,rs1,shamt \\ +\multicolumn{1}{c|}{rd} & MUL.D rd,rs1,rs2[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{111} & -\multicolumn{2}{c|}{000010} & -\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRLI rd,rs1,shamt \\ +\multicolumn{1}{c|}{rd} & DIV.D rd,rs1,rs2[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110100} & -\multicolumn{2}{c|}{111} & -\multicolumn{2}{c|}{000011} & -\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRAI rd,rs1,shamt \\ +\multicolumn{1}{c|}{rd} & SQRT.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & ADD rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & SGNINJ.D rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0000000001} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SUB rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & SGNINJN.D rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0000000010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLT rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & SGNMUL.D rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0000000011} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLTU rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVT.L.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0000000100} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & AND rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVTU.L.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0000000101} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & OR rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVT.W.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0000000110} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & XOR rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVTU.W.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0000000111} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & NOR rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVT.L.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{1110000010} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLL rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVTU.L.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{1110000100} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRL rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVT.W.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{1110000110} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRA rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVTU.W.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0010000000} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & MUL rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & CVT.S.L rd,rs1[,rm] \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVTU.S.L rd,rs1[,rm] \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVT.S.W rd,rs1[,rm] \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVTU.S.W rd,rs1[,rm] \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVT.D.L rd,rs1[,rm] \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVTU.D.L rd,rs1[,rm] \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVT.D.W rd,rs1 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVTU.D.W rd,rs1 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{00010} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVT.S.D rd,rs1[,rm] \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & CVT.D.S rd,rs1 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0010000010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & MULH rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & C.EQ.S rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0010000011} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & MULHU rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & C.LT.S rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0010000100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & DIV rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & C.LE.S rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0010000101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & DIVU rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & C.EQ.D rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0010000110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & REM rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & C.LT.D rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110101} & -\multicolumn{5}{c|}{0010000111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & REMU rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & C.LE.D rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{9}{c}{} & \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & MFF.S rd,rs2 \\ +\cline{2-10} + + & -\multicolumn{9}{c}{\bf 32-bit Integer Compute Instructions} & \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & MFF.D rd,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110110} & -\multicolumn{2}{c|}{000} & -\multicolumn{4}{c|}{imm12} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & ADDIW rd,rs1,imm12 \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & MFFL.D rd,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110110} & -\multicolumn{2}{c|}{111} & -\multicolumn{2}{c|}{000001} & -\multicolumn{1}{c|}{0} & -\multicolumn{1}{c|}{shamtw} & -\multicolumn{1}{c|}{rd} & -\multicolumn{1}{c|}{rs1} & SLLIW rd,rs1,shamtw \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rd} & MFFH.D rd,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110110} & -\multicolumn{2}{c|}{111} & -\multicolumn{2}{c|}{000010} & -\multicolumn{1}{c|}{0} & -\multicolumn{1}{c|}{shamtw} & -\multicolumn{1}{c|}{rd} & -\multicolumn{1}{c|}{rs1} & SRLIW rd,rs1,shamtw \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MTF.S rd,rs1 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110110} & -\multicolumn{2}{c|}{111} & -\multicolumn{2}{c|}{000011} & -\multicolumn{1}{c|}{0} & -\multicolumn{1}{c|}{shamtw} & -\multicolumn{1}{c|}{rd} & -\multicolumn{1}{c|}{rs1} & SRAIW rd,rs1,shamtw \\ +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & MTF.D rd,rs1 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & ADDW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & MTFLH.D rd,rs1,rs2 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0000000001} & -\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SUBW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & L.S rd,rs1,imm12 \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{1110000010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & L.D rd,rs1,imm12 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLLW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{imm12lo} & S.S imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{1110000100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRLW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{imm12lo} & S.D imm12hi,rs1,rs2,imm12lo \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{1110000110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRAW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & MADD.S rd,rs1,rs2,rs3[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0010000000} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & MULW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & MSUB.S rd,rs1,rs2,rs3[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0010000010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & MULHW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & NMSUB.S rd,rs1,rs2,rs3[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0010000011} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & MULHUW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & NMADD.S rd,rs1,rs2,rs3[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0010000100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & DIVW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & MADD.D rd,rs1,rs2,rs3[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0010000101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & DIVUW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & MSUB.D rd,rs1,rs2,rs3[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0010000110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & REMW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & NMSUB.D rd,rs1,rs2,rs3[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1110111} & -\multicolumn{5}{c|}{0010000111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & +\multicolumn{2}{c|}{rm} & +\multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & REMUW rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & NMADD.D rd,rs1,rs2,rs3[,rm] \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Control Transfer Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Memory Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Atomic Memory Instructions} & \\ \cline{2-10} @@ -1027,45 +1626,97 @@ & \multicolumn{9}{c}{} & \\ & -\multicolumn{9}{c}{\bf Floating-Point Memory Instructions} & \\ +\multicolumn{9}{c}{\bf Integer Compute Instructions} & \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101000} & -\multicolumn{2}{c|}{010} & -\multicolumn{4}{c|}{imm12} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & L.S rd,rs1,imm12 \\ +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf 32-bit Integer Compute Instructions} & \\ \cline{2-10} +\end{tabular} +\end{center} +\end{small} + +\label{instr-table} +\end{table} + + +\newpage + +\begin{table}[p] +\begin{small} +\begin{center} +\begin{tabular}{rcccccccccl} + & +\hspace*{0.6in} & +\hspace*{0.3in} & +\hspace*{0.1in} & +\hspace*{0.2in} & +\hspace*{0.2in} & +\hspace*{0.1in} & +\hspace*{0.3in} & +\hspace*{0.3in} & +\hspace*{0.3in} \\ + & +\instbitrange{31}{25} & +\instbitrange{24}{23} & +\instbit{22} & +\instbitrange{21}{20} & +\instbitrange{19}{16} & +\instbit{15} & +\instbitrange{14}{10} & +\instbitrange{9}{5} & +\instbitrange{4}{0} \\ +\cline{2-10} & -\multicolumn{1}{|c|}{1101000} & -\multicolumn{2}{c|}{011} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{8}{c|}{jump target} & J-type \\ +\cline{2-10} +& +\multicolumn{1}{|c|}{opcode} & +\multicolumn{7}{c|}{LUI-immediate} & +\multicolumn{1}{c|}{rd} & LUI-type \\ +\cline{2-10} +& +\multicolumn{1}{|c|}{opcode} & +\multicolumn{2}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & L.D rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & I-type \\ \cline{2-10} - - & -\multicolumn{1}{|c|}{1101001} & -\multicolumn{2}{c|}{010} & -\multicolumn{3}{c|}{imm12hi} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{2}{c|}{funct3} & +\multicolumn{3}{c|}{immed[11:5]} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & S.S rs2,rs1,imm12 \\ +\multicolumn{1}{c|}{immed[4:0]} & B-type \\ \cline{2-10} - - & -\multicolumn{1}{|c|}{1101001} & -\multicolumn{2}{c|}{011} & -\multicolumn{3}{c|}{imm12hi} & +\multicolumn{1}{|c|}{opcode} & +\multicolumn{5}{c|}{funct10} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm12lo} & S.D rs2,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & R-type \\ +\cline{2-10} +& +\multicolumn{1}{|c|}{opcode} & +\multicolumn{3}{c|}{funct5} & +\multicolumn{2}{c|}{rs3} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rd} & R4-type \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Floating-Point Memory Instructions} & \\ \cline{2-10} @@ -1077,7 +1728,7 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{00000} & @@ -1088,10 +1739,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{00001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SUB.S rd,rs1,rs2[,rm] \\ @@ -1099,10 +1750,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{00010} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & MUL.S rd,rs1,rs2[,rm] \\ @@ -1110,10 +1761,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{00011} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & DIV.S rd,rs1,rs2[,rm] \\ @@ -1121,10 +1772,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{00100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SQRT.S rd,rs1[,rm] \\ @@ -1132,8 +1783,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & @@ -1143,10 +1794,10 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{00001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SUB.D rd,rs1,rs2[,rm] \\ @@ -1154,10 +1805,10 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{00010} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & MUL.D rd,rs1,rs2[,rm] \\ @@ -1165,10 +1816,10 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{00011} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & DIV.D rd,rs1,rs2[,rm] \\ @@ -1176,10 +1827,10 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{00100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SQRT.D rd,rs1[,rm] \\ @@ -1187,7 +1838,7 @@ & -\multicolumn{1}{|c|}{1101100} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & @@ -1198,7 +1849,7 @@ & -\multicolumn{1}{|c|}{1101101} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & @@ -1209,7 +1860,7 @@ & -\multicolumn{1}{|c|}{1101110} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & @@ -1220,7 +1871,7 @@ & -\multicolumn{1}{|c|}{1101111} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & @@ -1231,8 +1882,8 @@ & -\multicolumn{1}{|c|}{1101100} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & @@ -1242,8 +1893,8 @@ & -\multicolumn{1}{|c|}{1101101} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & @@ -1253,8 +1904,8 @@ & -\multicolumn{1}{|c|}{1101110} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & @@ -1264,8 +1915,8 @@ & -\multicolumn{1}{|c|}{1101111} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rs2} & @@ -1358,8 +2009,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{0000000101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SGNINJ.S rd,rs1,rs2 \\ @@ -1367,8 +2018,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{0000000110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SGNINJN.S rd,rs1,rs2 \\ @@ -1376,8 +2027,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{0000000111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SGNMUL.S rd,rs1,rs2 \\ @@ -1385,8 +2036,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100000101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SGNINJ.D rd,rs1,rs2 \\ @@ -1394,8 +2045,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100000110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SGNINJN.D rd,rs1,rs2 \\ @@ -1403,8 +2054,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100000111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SGNMUL.D rd,rs1,rs2 \\ @@ -1412,10 +2063,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{10011} & +\multicolumn{2}{c|}{00010} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVT.S.D rd,rs1[,rm] \\ @@ -1423,8 +2074,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100010000} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVT.D.S rd,rs1 \\ @@ -1439,10 +2090,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01100} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVT.S.L rd,rs1[,rm] \\ @@ -1450,10 +2101,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01101} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVTU.S.L rd,rs1[,rm] \\ @@ -1461,10 +2112,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01110} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVT.S.W rd,rs1[,rm] \\ @@ -1472,10 +2123,10 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01111} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVTU.S.W rd,rs1[,rm] \\ @@ -1483,10 +2134,10 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01100} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVT.D.L rd,rs1[,rm] \\ @@ -1494,10 +2145,10 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01101} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVTU.D.L rd,rs1[,rm] \\ @@ -1505,8 +2156,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100001110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVT.D.W rd,rs1 \\ @@ -1514,8 +2165,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100001111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & CVTU.D.W rd,rs1 \\ @@ -1523,8 +2174,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1101111100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & MTFLH.D rd,rs1,rs2 \\ @@ -1532,8 +2183,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{0001011100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & MTF.S rd,rs1 \\ @@ -1541,8 +2192,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1101011100} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & MTF.D rd,rs1 \\ @@ -1557,96 +2208,96 @@ & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & CVT.L.S rm,rd,rs1 \\ +\multicolumn{1}{c|}{rd} & CVT.L.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01001} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & CVTU.L.S rm,rd,rs1 \\ +\multicolumn{1}{c|}{rd} & CVTU.L.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01010} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & CVT.W.S rm,rd,rs1 \\ +\multicolumn{1}{c|}{rd} & CVT.W.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101010} & +\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01011} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & CVTU.W.S rm,rd,rs1 \\ +\multicolumn{1}{c|}{rd} & CVTU.W.S rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & CVT.L.D rm,rd,rs1 \\ +\multicolumn{1}{c|}{rd} & CVT.L.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01001} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & CVTU.L.D rm,rd,rs1 \\ +\multicolumn{1}{c|}{rd} & CVTU.L.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01010} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & CVT.W.D rm,rd,rs1 \\ +\multicolumn{1}{c|}{rd} & CVT.W.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{1}{c|}{11} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & -\multicolumn{2}{c|}{01011} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & CVTU.W.D rm,rd,rs1 \\ +\multicolumn{1}{c|}{rd} & CVTU.W.D rd,rs1[,rm] \\ \cline{2-10} & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1101011001} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rd} & MFFL.D rd,rs2 \\ @@ -1654,8 +2305,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1101011010} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rd} & MFFH.D rd,rs2 \\ @@ -1663,8 +2314,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{0001011000} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rd} & MFF.S rd,rs2 \\ @@ -1672,8 +2323,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1101011000} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000011} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rd} & MFF.D rd,rs2 \\ @@ -1764,8 +2415,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{0000010101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & C.EQ.S rd,rs1,rs2 \\ @@ -1773,8 +2424,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{0000010110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & C.LT.S rd,rs1,rs2 \\ @@ -1782,8 +2433,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{0000010111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & C.LE.S rd,rs1,rs2 \\ @@ -1791,8 +2442,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100010101} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & C.EQ.D rd,rs1,rs2 \\ @@ -1800,8 +2451,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100010110} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & C.LT.D rd,rs1,rs2 \\ @@ -1809,8 +2460,8 @@ & -\multicolumn{1}{|c|}{1101010} & -\multicolumn{5}{c|}{1100010111} & +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & C.LE.D rd,rs1,rs2 \\ @@ -1825,102 +2476,12 @@ & -\multicolumn{1}{|c|}{1111011} & -\multicolumn{5}{c|}{0000000000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rd} & RDNPC rd \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1111011} & -\multicolumn{5}{c|}{0010000000} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rd} & MFCR rd,rs2 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1111011} & -\multicolumn{5}{c|}{0010000001} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & MTCR rs1,rs2 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1111011} & -\multicolumn{5}{c|}{0100000000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & SYNC \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1111011} & -\multicolumn{2}{c|}{011} & -\multicolumn{4}{c|}{imm12} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & SYSCALL imm12 \\ -\cline{2-10} - - -& \multicolumn{9}{c}{} & \\ & \multicolumn{9}{c}{\bf Privileged Instructions} & \\ \cline{2-10} -& -\multicolumn{1}{|c|}{1101011} & -\multicolumn{5}{c|}{0000000000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rd} & EI rd \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1101011} & -\multicolumn{5}{c|}{0000000001} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rd} & DI rd \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1101011} & -\multicolumn{5}{c|}{0010000000} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rd} & MFPCR rd,rs2 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1101011} & -\multicolumn{5}{c|}{0010000001} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & MTPCR rs1,rs2 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{1101011} & -\multicolumn{5}{c|}{0100000000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & ERET \\ -\cline{2-10} - - \end{tabular} \end{center} \end{small} @@ -2,197 +2,195 @@ # <instruction name> <opcode> <args> # # <opcode> is given by specifying one or more range/value pairs: -# highbit..lowbit=value (e.g. 31..25=0x45 24..22=0x0) +# highbit..lowbit=value (e.g. 6..0=0x45 9..7=0x0) # # <args> is one of xa,xb,xc,fa,fb,fc,fd,imm,imm20,imm27,shamt,shamtw unimp 31..0=0 -j 31..25=0x60 imm25 -jal 31..25=0x61 imm25 - -jalr.c 31..25=0x62 24..22=0 rd rs1 imm12 -jalr.r 31..25=0x62 24..22=1 rd rs1 imm12 -jalr.j 31..25=0x62 24..22=2 rd rs1 imm12 - -beq 31..25=0x63 24..22=0 rs1 rs2 imm12lo imm12hi -bne 31..25=0x63 24..22=1 rs1 rs2 imm12lo imm12hi -blt 31..25=0x63 24..22=4 rs1 rs2 imm12lo imm12hi -bge 31..25=0x63 24..22=5 rs1 rs2 imm12lo imm12hi -bltu 31..25=0x63 24..22=6 rs1 rs2 imm12lo imm12hi -bgeu 31..25=0x63 24..22=7 rs1 rs2 imm12lo imm12hi - -lui 31..25=0x71 rd imm20 - -addi 31..25=0x74 24..22=0 rd rs1 imm12 -slti 31..25=0x74 24..22=2 rd rs1 imm12 -sltiu 31..25=0x74 24..22=3 rd rs1 imm12 -andi 31..25=0x74 24..22=4 rd rs1 imm12 -ori 31..25=0x74 24..22=5 rd rs1 imm12 -xori 31..25=0x74 24..22=6 rd rs1 imm12 -slli 31..25=0x74 24..22=7 21..16=1 rd rs1 shamt -srli 31..25=0x74 24..22=7 21..16=2 rd rs1 shamt -srai 31..25=0x74 24..22=7 21..16=3 rd rs1 shamt - -add 31..25=0x75 24..22=0 21..15=0 rd rs1 rs2 -sub 31..25=0x75 24..22=0 21..15=1 rd rs1 rs2 -slt 31..25=0x75 24..22=0 21..15=2 rd rs1 rs2 -sltu 31..25=0x75 24..22=0 21..15=3 rd rs1 rs2 -and 31..25=0x75 24..22=0 21..15=4 rd rs1 rs2 -or 31..25=0x75 24..22=0 21..15=5 rd rs1 rs2 -xor 31..25=0x75 24..22=0 21..15=6 rd rs1 rs2 -nor 31..25=0x75 24..22=0 21..15=7 rd rs1 rs2 -sll 31..25=0x75 24..22=7 21..16=1 15=0 rd rs1 rs2 -srl 31..25=0x75 24..22=7 21..16=2 15=0 rd rs1 rs2 -sra 31..25=0x75 24..22=7 21..16=3 15=0 rd rs1 rs2 - -mul 31..25=0x75 24..22=1 21..15=0 rd rs1 rs2 -mulh 31..25=0x75 24..22=1 21..15=2 rd rs1 rs2 -mulhu 31..25=0x75 24..22=1 21..15=3 rd rs1 rs2 -div 31..25=0x75 24..22=1 21..15=4 rd rs1 rs2 -divu 31..25=0x75 24..22=1 21..15=5 rd rs1 rs2 -rem 31..25=0x75 24..22=1 21..15=6 rd rs1 rs2 -remu 31..25=0x75 24..22=1 21..15=7 rd rs1 rs2 - - - -addiw 31..25=0x76 24..22=0 rd rs1 imm12 -slliw 31..25=0x76 24..22=7 21..16=1 15=0 rd rs1 shamtw -srliw 31..25=0x76 24..22=7 21..16=2 15=0 rd rs1 shamtw -sraiw 31..25=0x76 24..22=7 21..16=3 15=0 rd rs1 shamtw - -addw 31..25=0x77 24..22=0 21..15=0 rd rs1 rs2 -subw 31..25=0x77 24..22=0 21..15=1 rd rs1 rs2 -sllw 31..25=0x77 24..22=7 21..16=1 15=0 rd rs1 rs2 -srlw 31..25=0x77 24..22=7 21..16=2 15=0 rd rs1 rs2 -sraw 31..25=0x77 24..22=7 21..16=3 15=0 rd rs1 rs2 - -mulw 31..25=0x77 24..22=1 21..15=0 rd rs1 rs2 -mulhw 31..25=0x77 24..22=1 21..15=2 rd rs1 rs2 -mulhuw 31..25=0x77 24..22=1 21..15=3 rd rs1 rs2 -divw 31..25=0x77 24..22=1 21..15=4 rd rs1 rs2 -divuw 31..25=0x77 24..22=1 21..15=5 rd rs1 rs2 -remw 31..25=0x77 24..22=1 21..15=6 rd rs1 rs2 -remuw 31..25=0x77 24..22=1 21..15=7 rd rs1 rs2 - -lb 31..25=0x78 24..22=0 rd rs1 imm12 -lh 31..25=0x78 24..22=1 rd rs1 imm12 -lw 31..25=0x78 24..22=2 rd rs1 imm12 -ld 31..25=0x78 24..22=3 rd rs1 imm12 -lbu 31..25=0x78 24..22=4 rd rs1 imm12 -lhu 31..25=0x78 24..22=5 rd rs1 imm12 -lwu 31..25=0x78 24..22=6 rd rs1 imm12 -synci 31..25=0x78 24..22=7 4..0=0 rs1 imm12 +j imm25 6..0=0x60 +jal imm25 6..0=0x61 + +jalr.c rd rs1 imm12 9..7=0 6..0=0x62 +jalr.r rd rs1 imm12 9..7=1 6..0=0x62 +jalr.j rd rs1 imm12 9..7=2 6..0=0x62 + +beq imm12hi rs1 rs2 imm12lo 9..7=0 6..0=0x63 +bne imm12hi rs1 rs2 imm12lo 9..7=1 6..0=0x63 +blt imm12hi rs1 rs2 imm12lo 9..7=4 6..0=0x63 +bge imm12hi rs1 rs2 imm12lo 9..7=5 6..0=0x63 +bltu imm12hi rs1 rs2 imm12lo 9..7=6 6..0=0x63 +bgeu imm12hi rs1 rs2 imm12lo 9..7=7 6..0=0x63 + +lui rd imm20 6..0=0x71 + +addi rd rs1 imm12 9..7=0 6..0=0x74 +slti rd rs1 imm12 9..7=2 6..0=0x74 +sltiu rd rs1 imm12 9..7=3 6..0=0x74 +andi rd rs1 imm12 9..7=4 6..0=0x74 +ori rd rs1 imm12 9..7=5 6..0=0x74 +xori rd rs1 imm12 9..7=6 6..0=0x74 +slli rd rs1 shamt 15..10=1 9..7=7 6..0=0x74 +srli rd rs1 shamt 15..10=2 9..7=7 6..0=0x74 +srai rd rs1 shamt 15..10=3 9..7=7 6..0=0x74 + +add rd rs1 rs2 16..10=0 9..7=0 6..0=0x75 +sub rd rs1 rs2 16..10=1 9..7=0 6..0=0x75 +slt rd rs1 rs2 16..10=2 9..7=0 6..0=0x75 +sltu rd rs1 rs2 16..10=3 9..7=0 6..0=0x75 +and rd rs1 rs2 16..10=4 9..7=0 6..0=0x75 +or rd rs1 rs2 16..10=5 9..7=0 6..0=0x75 +xor rd rs1 rs2 16..10=6 9..7=0 6..0=0x75 +nor rd rs1 rs2 16..10=7 9..7=0 6..0=0x75 +sll rd rs1 rs2 16=0 15..10=1 9..7=7 6..0=0x75 +srl rd rs1 rs2 16=0 15..10=2 9..7=7 6..0=0x75 +sra rd rs1 rs2 16=0 15..10=3 9..7=7 6..0=0x75 + +mul rd rs1 rs2 16..10=0 9..7=1 6..0=0x75 +mulh rd rs1 rs2 16..10=2 9..7=1 6..0=0x75 +mulhu rd rs1 rs2 16..10=3 9..7=1 6..0=0x75 +div rd rs1 rs2 16..10=4 9..7=1 6..0=0x75 +divu rd rs1 rs2 16..10=5 9..7=1 6..0=0x75 +rem rd rs1 rs2 16..10=6 9..7=1 6..0=0x75 +remu rd rs1 rs2 16..10=7 9..7=1 6..0=0x75 + +addiw rd rs1 imm12 9..7=0 6..0=0x76 +slliw rd rs1 21=0 shamtw 15..10=1 9..7=7 6..0=0x76 +srliw rd rs1 21=0 shamtw 15..10=2 9..7=7 6..0=0x76 +sraiw rd rs1 21=0 shamtw 15..10=3 9..7=7 6..0=0x76 + +addw rd rs1 rs2 16..10=0 9..7=0 6..0=0x77 +subw rd rs1 rs2 16..10=1 9..7=0 6..0=0x77 +sllw rd rs1 rs2 16=0 15..10=1 9..7=7 6..0=0x77 +srlw rd rs1 rs2 16=0 15..10=2 9..7=7 6..0=0x77 +sraw rd rs1 rs2 16=0 15..10=3 9..7=7 6..0=0x77 + +mulw rd rs1 rs2 16..10=0 9..7=1 6..0=0x77 +mulhw rd rs1 rs2 16..10=2 9..7=1 6..0=0x77 +mulhuw rd rs1 rs2 16..10=3 9..7=1 6..0=0x77 +divw rd rs1 rs2 16..10=4 9..7=1 6..0=0x77 +divuw rd rs1 rs2 16..10=5 9..7=1 6..0=0x77 +remw rd rs1 rs2 16..10=6 9..7=1 6..0=0x77 +remuw rd rs1 rs2 16..10=7 9..7=1 6..0=0x77 + +lb rd rs1 imm12 9..7=0 6..0=0x78 +lh rd rs1 imm12 9..7=1 6..0=0x78 +lw rd rs1 imm12 9..7=2 6..0=0x78 +ld rd rs1 imm12 9..7=3 6..0=0x78 +lbu rd rs1 imm12 9..7=4 6..0=0x78 +lhu rd rs1 imm12 9..7=5 6..0=0x78 +lwu rd rs1 imm12 9..7=6 6..0=0x78 +synci 31..27=0 rs1 imm12 9..7=7 6..0=0x78 # NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c # and elfxx-mips.c to detect them. this is a hack to handle the split immed. # just open up those files and search for MATCH_SW; should be obvious. -sb 31..25=0x79 24..22=0 rs2 rs1 imm12lo imm12hi -sh 31..25=0x79 24..22=1 rs2 rs1 imm12lo imm12hi -sw 31..25=0x79 24..22=2 rs2 rs1 imm12lo imm12hi -sd 31..25=0x79 24..22=3 rs2 rs1 imm12lo imm12hi - -amow.add 31..25=0x7A 24..22=2 21..15=0 rd rs1 rs2 -amow.swap 31..25=0x7A 24..22=2 21..15=1 rd rs1 rs2 -amow.and 31..25=0x7A 24..22=2 21..15=2 rd rs1 rs2 -amow.or 31..25=0x7A 24..22=2 21..15=3 rd rs1 rs2 -amow.min 31..25=0x7A 24..22=2 21..15=4 rd rs1 rs2 -amow.max 31..25=0x7A 24..22=2 21..15=5 rd rs1 rs2 -amow.minu 31..25=0x7A 24..22=2 21..15=6 rd rs1 rs2 -amow.maxu 31..25=0x7A 24..22=2 21..15=7 rd rs1 rs2 - -amo.add 31..25=0x7A 24..22=3 21..15=0 rd rs1 rs2 -amo.swap 31..25=0x7A 24..22=3 21..15=1 rd rs1 rs2 -amo.and 31..25=0x7A 24..22=3 21..15=2 rd rs1 rs2 -amo.or 31..25=0x7A 24..22=3 21..15=3 rd rs1 rs2 -amo.min 31..25=0x7A 24..22=3 21..15=4 rd rs1 rs2 -amo.max 31..25=0x7A 24..22=3 21..15=5 rd rs1 rs2 -amo.minu 31..25=0x7A 24..22=3 21..15=6 rd rs1 rs2 -amo.maxu 31..25=0x7A 24..22=3 21..15=7 rd rs1 rs2 - -rdnpc 31..25=0x7B 24..22=0 21..15=0 14..5=0 rd -mfcr 31..25=0x7B 24..22=1 21..15=0 9..5=0 rd rs2 -mtcr 31..25=0x7B 24..22=1 21..15=1 4..0=0 rs1 rs2 -sync 31..25=0x7B 24..22=2 21..15=0 14..0=0 -syscall 31..25=0x7B 24..22=3 9..0=0 imm12 - -ei 31..25=0x6B 24..22=0 21..15=0 14..5=0 rd -di 31..25=0x6B 24..22=0 21..15=1 14..5=0 rd -mfpcr 31..25=0x6B 24..22=1 21..15=0 9..5=0 rd rs2 -mtpcr 31..25=0x6B 24..22=1 21..15=1 4..0=0 rs1 rs2 -eret 31..25=0x6B 24..22=2 21..15=0 14..0=0 +sb imm12hi rs1 rs2 imm12lo 9..7=0 6..0=0x79 +sh imm12hi rs1 rs2 imm12lo 9..7=1 6..0=0x79 +sw imm12hi rs1 rs2 imm12lo 9..7=2 6..0=0x79 +sd imm12hi rs1 rs2 imm12lo 9..7=3 6..0=0x79 + +amow.add rd rs1 rs2 16..10=0 9..7=2 6..0=0x7A +amow.swap rd rs1 rs2 16..10=1 9..7=2 6..0=0x7A +amow.and rd rs1 rs2 16..10=2 9..7=2 6..0=0x7A +amow.or rd rs1 rs2 16..10=3 9..7=2 6..0=0x7A +amow.min rd rs1 rs2 16..10=4 9..7=2 6..0=0x7A +amow.max rd rs1 rs2 16..10=5 9..7=2 6..0=0x7A +amow.minu rd rs1 rs2 16..10=6 9..7=2 6..0=0x7A +amow.maxu rd rs1 rs2 16..10=7 9..7=2 6..0=0x7A + +amo.add rd rs1 rs2 16..10=0 9..7=3 6..0=0x7A +amo.swap rd rs1 rs2 16..10=1 9..7=3 6..0=0x7A +amo.and rd rs1 rs2 16..10=2 9..7=3 6..0=0x7A +amo.or rd rs1 rs2 16..10=3 9..7=3 6..0=0x7A +amo.min rd rs1 rs2 16..10=4 9..7=3 6..0=0x7A +amo.max rd rs1 rs2 16..10=5 9..7=3 6..0=0x7A +amo.minu rd rs1 rs2 16..10=6 9..7=3 6..0=0x7A +amo.maxu rd rs1 rs2 16..10=7 9..7=3 6..0=0x7A + +rdnpc rd 26..17=0 16..10=0 9..7=0 6..0=0x7B +mfcr rd 26..22=0 rs2 16..10=0 9..7=1 6..0=0x7B +mtcr 31..27=0 rs1 rs2 16..10=1 9..7=1 6..0=0x7B +sync 31..17=0 16..10=0 9..7=2 6..0=0x7B +syscall 31..22=0 imm12 9..7=3 6..0=0x7B + +ei rd 26..17=0 16..10=0 9..7=0 6..0=0x6B +di rd 26..17=0 16..10=1 9..7=0 6..0=0x6B +mfpcr rd 26..22=0 rs2 16..10=0 9..7=1 6..0=0x6B +mtpcr 31..27=0 rs1 rs2 16..10=1 9..7=1 6..0=0x6B +eret 31..17=0 16..10=0 9..7=2 6..0=0x6B # 0x7C-0x7F are reserved for >32b instructions -add.s 31..25=0x6A 24..23=0 19..15=0 rd rs1 rs2 rm -sub.s 31..25=0x6A 24..23=0 19..15=1 rd rs1 rs2 rm -mul.s 31..25=0x6A 24..23=0 19..15=2 rd rs1 rs2 rm -div.s 31..25=0x6A 24..23=0 19..15=3 rd rs1 rs2 rm -sqrt.s 31..25=0x6A 24..23=0 19..15=4 14..10=0 rd rs1 rm -sgninj.s 31..25=0x6A 24..23=0 22..20=0 19..15=5 rd rs1 rs2 -sgninjn.s 31..25=0x6A 24..23=0 22..20=0 19..15=6 rd rs1 rs2 -sgnmul.s 31..25=0x6A 24..23=0 22..20=0 19..15=7 rd rs1 rs2 - -add.d 31..25=0x6A 24..23=3 19..15=0x0 rd rs1 rs2 rm -sub.d 31..25=0x6A 24..23=3 19..15=0x1 rd rs1 rs2 rm -mul.d 31..25=0x6A 24..23=3 19..15=0x2 rd rs1 rs2 rm -div.d 31..25=0x6A 24..23=3 19..15=0x3 rd rs1 rs2 rm -sqrt.d 31..25=0x6A 24..23=3 19..15=0x4 14..10=0 rd rs1 rm -sgninj.d 31..25=0x6A 24..23=3 22..20=0 19..15=0x5 rd rs1 rs2 -sgninjn.d 31..25=0x6A 24..23=3 22..20=0 19..15=0x6 rd rs1 rs2 -sgnmul.d 31..25=0x6A 24..23=3 22..20=0 19..15=0x7 rd rs1 rs2 - -cvt.l.s 31..25=0x6A 24..23=0 19..15=0x8 14..10=0 rm rd rs1 -cvtu.l.s 31..25=0x6A 24..23=0 19..15=0x9 14..10=0 rm rd rs1 -cvt.w.s 31..25=0x6A 24..23=0 19..15=0xA 14..10=0 rm rd rs1 -cvtu.w.s 31..25=0x6A 24..23=0 19..15=0xB 14..10=0 rm rd rs1 - -cvt.l.d 31..25=0x6A 24..23=3 19..15=0x8 14..10=0 rm rd rs1 -cvtu.l.d 31..25=0x6A 24..23=3 19..15=0x9 14..10=0 rm rd rs1 -cvt.w.d 31..25=0x6A 24..23=3 19..15=0xA 14..10=0 rm rd rs1 -cvtu.w.d 31..25=0x6A 24..23=3 19..15=0xB 14..10=0 rm rd rs1 - -cvt.s.l 31..25=0x6A 24..23=0 19..15=0xC 14..10=0 rd rs1 rm -cvtu.s.l 31..25=0x6A 24..23=0 19..15=0xD 14..10=0 rd rs1 rm -cvt.s.w 31..25=0x6A 24..23=0 19..15=0xE 14..10=0 rd rs1 rm -cvtu.s.w 31..25=0x6A 24..23=0 19..15=0xF 14..10=0 rd rs1 rm - -cvt.d.l 31..25=0x6A 24..23=3 19..15=0xC 14..10=0 rd rs1 rm -cvtu.d.l 31..25=0x6A 24..23=3 19..15=0xD 14..10=0 rd rs1 rm -cvt.d.w 31..25=0x6A 24..23=3 22..20=0 19..15=0xE 14..10=0 rd rs1 -cvtu.d.w 31..25=0x6A 24..23=3 22..20=0 19..15=0xF 14..10=0 rd rs1 - -cvt.s.d 31..25=0x6A 24..23=0 19..15=0x13 14..10=0 rd rs1 rm -cvt.d.s 31..25=0x6A 24..23=3 22..20=0 19..15=0x10 14..10=0 rd rs1 - -c.eq.s 31..25=0x6A 24..23=0 22..20=0 19..15=0x15 rd rs1 rs2 -c.lt.s 31..25=0x6A 24..23=0 22..20=0 19..15=0x16 rd rs1 rs2 -c.le.s 31..25=0x6A 24..23=0 22..20=0 19..15=0x17 rd rs1 rs2 - -c.eq.d 31..25=0x6A 24..23=3 22..20=0 19..15=0x15 rd rs1 rs2 -c.lt.d 31..25=0x6A 24..23=3 22..20=0 19..15=0x16 rd rs1 rs2 -c.le.d 31..25=0x6A 24..23=3 22..20=0 19..15=0x17 rd rs1 rs2 - -mff.s 31..25=0x6A 9..5=0 24..23=0 22..20=2 19..15=0x18 rd rs2 -mff.d 31..25=0x6A 9..5=0 24..23=3 22..20=2 19..15=0x18 rd rs2 -mffl.d 31..25=0x6A 9..5=0 24..23=3 22..20=2 19..15=0x19 rd rs2 -mffh.d 31..25=0x6A 9..5=0 24..23=3 22..20=2 19..15=0x1A rd rs2 -mtf.s 31..25=0x6A 14..10=0 24..23=0 22..20=2 19..15=0x1C rd rs1 -mtf.d 31..25=0x6A 14..10=0 24..23=3 22..20=2 19..15=0x1C rd rs1 -mtflh.d 31..25=0x6A 24..23=3 22..20=3 19..15=0x1C rd rs1 rs2 - -l.s 31..25=0x68 24..22=2 rd rs1 imm12 -l.d 31..25=0x68 24..22=3 rd rs1 imm12 - -s.s 31..25=0x69 24..22=2 rs2 rs1 imm12lo imm12hi -s.d 31..25=0x69 24..22=3 rs2 rs1 imm12lo imm12hi - -madd.s 31..25=0x6C 24..23=0 rd rs1 rs2 rs3 rm -msub.s 31..25=0x6D 24..23=0 rd rs1 rs2 rs3 rm -nmsub.s 31..25=0x6E 24..23=0 rd rs1 rs2 rs3 rm -nmadd.s 31..25=0x6F 24..23=0 rd rs1 rs2 rs3 rm - -madd.d 31..25=0x6C 24..23=3 rd rs1 rs2 rs3 rm -msub.d 31..25=0x6D 24..23=3 rd rs1 rs2 rs3 rm -nmsub.d 31..25=0x6E 24..23=3 rd rs1 rs2 rs3 rm -nmadd.d 31..25=0x6F 24..23=3 rd rs1 rs2 rs3 rm +add.s rd rs1 rs2 16..12=0 rm 8..7=0 6..0=0x6A +sub.s rd rs1 rs2 16..12=1 rm 8..7=0 6..0=0x6A +mul.s rd rs1 rs2 16..12=2 rm 8..7=0 6..0=0x6A +div.s rd rs1 rs2 16..12=3 rm 8..7=0 6..0=0x6A +sqrt.s rd rs1 21..17=0 16..12=4 rm 8..7=0 6..0=0x6A +sgninj.s rd rs1 rs2 16..12=5 11..9=0 8..7=0 6..0=0x6A +sgninjn.s rd rs1 rs2 16..12=6 11..9=0 8..7=0 6..0=0x6A +sgnmul.s rd rs1 rs2 16..12=7 11..9=0 8..7=0 6..0=0x6A + +add.d rd rs1 rs2 16..12=0x0 rm 8..7=3 6..0=0x6A +sub.d rd rs1 rs2 16..12=0x1 rm 8..7=3 6..0=0x6A +mul.d rd rs1 rs2 16..12=0x2 rm 8..7=3 6..0=0x6A +div.d rd rs1 rs2 16..12=0x3 rm 8..7=3 6..0=0x6A +sqrt.d rd rs1 21..17=0 16..12=0x4 rm 8..7=3 6..0=0x6A +sgninj.d rd rs1 rs2 16..12=0x5 11..9=0 8..7=3 6..0=0x6A +sgninjn.d rd rs1 rs2 16..12=0x6 11..9=0 8..7=3 6..0=0x6A +sgnmul.d rd rs1 rs2 16..12=0x7 11..9=0 8..7=3 6..0=0x6A + +cvt.l.s rd rs1 21..17=0 16..12=0x8 rm 8..7=0 6..0=0x6A +cvtu.l.s rd rs1 21..17=0 16..12=0x9 rm 8..7=0 6..0=0x6A +cvt.w.s rd rs1 21..17=0 16..12=0xA rm 8..7=0 6..0=0x6A +cvtu.w.s rd rs1 21..17=0 16..12=0xB rm 8..7=0 6..0=0x6A + +cvt.l.d rd rs1 21..17=0 16..12=0x8 rm 8..7=3 6..0=0x6A +cvtu.l.d rd rs1 21..17=0 16..12=0x9 rm 8..7=3 6..0=0x6A +cvt.w.d rd rs1 21..17=0 16..12=0xA rm 8..7=3 6..0=0x6A +cvtu.w.d rd rs1 21..17=0 16..12=0xB rm 8..7=3 6..0=0x6A + +cvt.s.l rd rs1 21..17=0 16..12=0xC rm 8..7=0 6..0=0x6A +cvtu.s.l rd rs1 21..17=0 16..12=0xD rm 8..7=0 6..0=0x6A +cvt.s.w rd rs1 21..17=0 16..12=0xE rm 8..7=0 6..0=0x6A +cvtu.s.w rd rs1 21..17=0 16..12=0xF rm 8..7=0 6..0=0x6A + +cvt.d.l rd rs1 21..17=0 16..12=0xC rm 8..7=3 6..0=0x6A +cvtu.d.l rd rs1 21..17=0 16..12=0xD rm 8..7=3 6..0=0x6A +cvt.d.w rd rs1 21..17=0 16..12=0xE 11..9=0 8..7=3 6..0=0x6A +cvtu.d.w rd rs1 21..17=0 16..12=0xF 11..9=0 8..7=3 6..0=0x6A + +cvt.s.d rd rs1 21..17=0 16..12=0x13 rm 8..7=0 6..0=0x6A +cvt.d.s rd rs1 21..17=0 16..12=0x10 11..9=0 8..7=3 6..0=0x6A + +c.eq.s rd rs1 rs2 16..12=0x15 11..9=0 8..7=0 6..0=0x6A +c.lt.s rd rs1 rs2 16..12=0x16 11..9=0 8..7=0 6..0=0x6A +c.le.s rd rs1 rs2 16..12=0x17 11..9=0 8..7=0 6..0=0x6A + +c.eq.d rd rs1 rs2 16..12=0x15 11..9=0 8..7=3 6..0=0x6A +c.lt.d rd rs1 rs2 16..12=0x16 11..9=0 8..7=3 6..0=0x6A +c.le.d rd rs1 rs2 16..12=0x17 11..9=0 8..7=3 6..0=0x6A + +mff.s rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=0 6..0=0x6A +mff.d rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=3 6..0=0x6A +mffl.d rd 26..22=0 rs2 16..12=0x19 11..9=2 8..7=3 6..0=0x6A +mffh.d rd 26..22=0 rs2 16..12=0x1A 11..9=2 8..7=3 6..0=0x6A +mtf.s rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=0 6..0=0x6A +mtf.d rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=3 6..0=0x6A +mtflh.d rd rs1 rs2 16..12=0x1C 11..9=3 8..7=3 6..0=0x6A + +l.s rd rs1 imm12 9..7=2 6..0=0x68 +l.d rd rs1 imm12 9..7=3 6..0=0x68 + +s.s imm12hi rs1 rs2 imm12lo 9..7=2 6..0=0x69 +s.d imm12hi rs1 rs2 imm12lo 9..7=3 6..0=0x69 + +madd.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6C +msub.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6D +nmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6E +nmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6F + +madd.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6C +msub.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6D +nmsub.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6E +nmadd.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6F diff --git a/parse-opcodes b/parse-opcodes index 53409ea..ea234b9 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -11,18 +11,18 @@ arguments = {} types = {} arglut = {} -arglut['rs2'] = (14,10) -arglut['rs1'] = (9,5) -arglut['rd'] = (4,0) -arglut['rs3'] = (19,15) -arglut['imm25'] = (24,0) -arglut['imm20'] = (24,5) +arglut['rd'] = (31,27) +arglut['rs1'] = (26,22) +arglut['rs2'] = (21,17) +arglut['rs3'] = (16,12) +arglut['rm'] = (11,9) +arglut['imm25'] = (31,7) +arglut['imm20'] = (26,7) arglut['imm12'] = (21,10) -arglut['imm12lo'] = (4,0) -arglut['imm12hi'] = (21,15) -arglut['shamt'] = (15,10) -arglut['shamtw'] = (14,10) -arglut['rm'] = (22,20) +arglut['imm12hi'] = (31,27) +arglut['imm12lo'] = (16,10) +arglut['shamt'] = (21,16) +arglut['shamtw'] = (20,16) typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,10=b typelut[0x00] = 0 @@ -60,9 +60,9 @@ def make_disasm_table(match,mask): print '#define MASK_%s %s' % (name2, hex(mask[name])) def make_switch(match,mask): - opcode_base = 25 + opcode_base = 0 opcode_size = 7 - funct_base = 22 + funct_base = 7 funct_size = 3 opcode_mask = ((1<<(opcode_base+opcode_size))-(1<<opcode_base)) @@ -607,114 +607,114 @@ def print_verilog_j_type(name,match,arguments): print "`define %-10s 32'b%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - str_verilog_arg('imm25','',match,arguments) \ + str_verilog_arg('imm25','',match,arguments), \ + binary(yank(match,0,7),7) \ ) def print_verilog_lui_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ + str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('imm20','',match,arguments), \ - str_verilog_arg('rd','',match,arguments) \ + binary(yank(match,0,7),7) \ ) def print_verilog_b_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - binary(yank(match,22,3),3), \ str_verilog_arg('imm12hi','',match,arguments), \ - str_verilog_arg('rs2','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('imm12lo','',match,arguments) \ + str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('imm12lo','',match,arguments), \ + binary(yank(match,7,3),3), \ + binary(yank(match,0,7),7) \ ) def print_verilog_i_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - binary(yank(match,22,3),3), \ - str_verilog_arg('imm12','',match,arguments), \ + str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rd','',match,arguments) \ + str_verilog_arg('imm12','',match,arguments), \ + binary(yank(match,7,3),3), \ + binary(yank(match,0,7),7) \ ) def print_verilog_ish_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - binary(yank(match,22,3),3), \ - binary(yank(match,16,6),6), \ - str_verilog_arg('shamt','',match,arguments), \ + str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rd','',match,arguments) \ + str_verilog_arg('shamt','',match,arguments), \ + binary(yank(match,10,6),6), \ + binary(yank(match,7,3),3), \ + binary(yank(match,0,7),7) \ ) def print_verilog_ishw_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_0_%s_%s_%s" % \ + print "`define %-10s 32'b%s_%s_0_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - binary(yank(match,22,3),3), \ - binary(yank(match,16,6),6), \ - str_verilog_arg('shamtw','',match,arguments), \ + str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rd','',match,arguments) \ + str_verilog_arg('shamtw','',match,arguments), \ + binary(yank(match,10,6),6), \ + binary(yank(match,7,3),3), \ + binary(yank(match,0,7),7) \ ) def print_verilog_r4_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - binary(yank(match,22,3),3), \ - binary(yank(match,20,2),2), \ - str_verilog_arg('rs3','',match,arguments), \ - str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rd','',match,arguments) \ + str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rs3','',match,arguments), \ + binary(yank(match,9,3),3), \ + binary(yank(match,7,2),2), \ + binary(yank(match,0,7),7) \ ) def print_verilog_r4_rm_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - binary(yank(match,23,2),2), \ - str_verilog_arg('rm','',match,arguments), \ - str_verilog_arg('rs3','',match,arguments), \ - str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rd','',match,arguments) \ + str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rs3','',match,arguments), \ + str_verilog_arg('rm','',match,arguments), \ + binary(yank(match,7,2),2), \ + binary(yank(match,0,7),7) \ ) def print_verilog_r_rm_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - binary(yank(match,23,2),2), \ - str_verilog_arg('rm','',match,arguments), \ - binary(yank(match,15,5),5), \ - str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rd','',match,arguments) \ + str_verilog_arg('rs2','',match,arguments), \ + binary(yank(match,12,5),5), \ + str_verilog_arg('rm','',match,arguments), \ + binary(yank(match,7,2),2), \ + binary(yank(match,0,7),7) \ ) def print_verilog_r_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ - binary(yank(match,25,7),7), \ - binary(yank(match,15,10),10), \ - str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rd','',match,arguments), \ str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rd','',match,arguments) \ + str_verilog_arg('rs2','',match,arguments), \ + binary(yank(match,7,10),10), \ + binary(yank(match,0,7),7) \ ) def make_verilog(): @@ -795,7 +795,7 @@ for line in sys.stdin: mask[name] = mymask match[name] = mymatch - types[name] = typelut[yank(mymatch,25,7)] + types[name] = typelut[yank(mymatch,0,7)] if 'shamtw' in arguments[name]: types[name] = 7 elif 'imm12' in arguments[name]: |