[xcc,sim,opcodes] added more RVC instructions

3 files changed, 47 insertions, 5 deletions

diff --git a/inst.v b/inst.v
index 8dd27ee..95b4cd4 100644
--- a/inst.v
+++ b/inst.v
@@ -228,8 +228,8 @@
 `define VCFGIVL    32'b?????_?????_????????????_000_1110011
 `define SETVL      32'b?????_?????_000000000000_001_1110011
 `define VF         32'b00000_?????_????????????_010_1110011
-`define C_ADDI     32'b00000000000000000000000000000000
 `define C_LI       32'b00000000000000000000000000000000
+`define C_ADDI     32'b00000000000000000000000000000000
 `define C_MOVE     32'b00000000000000000000000000000000
 `define C_J        32'b00000000000000000000000000000000
 `define C_LDSP     32'b00000000000000000000000000000000
@@ -242,3 +242,22 @@
 `define C_SW       32'b00000000000000000000000000000000
 `define C_BEQ      32'b00000000000000000000000000000000
 `define C_BNE      32'b00000000000000000000000000000000
+`define C_LW0      32'b00000000000000000000000000000000
+`define C_LD0      32'b00000000000000000000000000000000
+`define C_FLW      32'b00000000000000000000000000000000
+`define C_FLD      32'b00000000000000000000000000000000
+`define C_FSW      32'b00000000000000000000000000000000
+`define C_FSD      32'b00000000000000000000000000000000
+`define C_SLLI     32'b00000000000000000000000000000000
+`define C_SLLI32   32'b00000000000000000000000000000000
+`define C_SRLI     32'b00000000000000000000000000000000
+`define C_SRLI32   32'b00000000000000000000000000000000
+`define C_SRAI     32'b00000000000000000000000000000000
+`define C_SRAI32   32'b00000000000000000000000000000000
+`define C_SLLIW    32'b00000000000000000000000000000000
+`define C_ADD      32'b00000000000000000000000000000000
+`define C_SUB      32'b00000000000000000000000000000000
+`define C_ADD3     32'b00000000000000000000000000000000
+`define C_SUB3     32'b00000000000000000000000000000000
+`define C_OR3      32'b00000000000000000000000000000000
+`define C_AND3     32'b00000000000000000000000000000000
diff --git a/opcodes b/opcodes
index 45e6483..364d289 100644
--- a/opcodes
+++ b/opcodes
@@ -318,8 +318,8 @@ setvl       rd       rs1 21..10=0 9..7=1     6..2=0x1C 1..0=3
 vf          31..27=0 rs1 imm12    9..7=2     6..2=0x1C 1..0=3
 
 # compressed instructions
-c.addi    cimm6    crd   4..0=0
-c.li      cimm6    crd   4..0=1
+c.li      cimm6    crd   4..0=0
+c.addi    cimm6    crd   4..0=1
 c.move 15=0 crs1   crd   4..0=2
 c.j    15=1   cimm10     4..0=2
 c.ldsp    cimm6    crd   4..0=4
@@ -328,7 +328,29 @@ c.sdsp    cimm6    crd   4..0=6
 c.swsp    cimm6    crd   4..0=8
 c.ld   crds  crs1s cimm5 4..0=9
 c.lw   crds  crs1s cimm5 4..0=10
-c.sd   crds  crs1s cimm5 4..0=12
-c.sw   crds  crs1s cimm5 4..0=13
+c.sd   crs2s crs1s cimm5 4..0=12
+c.sw   crs2s crs1s cimm5 4..0=13
 c.beq  crs2s crs1s cimm5 4..0=16
 c.bne  crs2s crs1s cimm5 4..0=17
+c.lw0 15=0 crs1    crd   4..0=18
+c.ld0 15=1 crs1    crd   4..0=18
+c.flw  crds  crs1s cimm5 4..0=20
+c.fld  crds  crs1s cimm5 4..0=21
+c.fsw  crs2s crs1s cimm5 4..0=22
+c.fsd  crs2s crs1s cimm5 4..0=24
+
+c.slli   crds 12..10=0 cimm5 4..0=25
+c.slli32 crds 12..10=1 cimm5 4..0=25
+c.srli   crds 12..10=2 cimm5 4..0=25
+c.srli32 crds 12..10=3 cimm5 4..0=25
+c.srai   crds 12..10=4 cimm5 4..0=25
+c.srai32 crds 12..10=5 cimm5 4..0=25
+c.slliw  crds 12..10=6 cimm5 4..0=25
+
+c.add crd crs1 15=0 4..0=26
+c.sub crd crs1 15=1 4..0=26
+
+c.add3 crds crs1s crs2bs 9..8=0 4..0=28
+c.sub3 crds crs1s crs2bs 9..8=1 4..0=28
+c.or3  crds crs1s crs2bs 9..8=2 4..0=28
+c.and3 crds crs1s crs2bs 9..8=3 4..0=28
diff --git a/parse-opcodes b/parse-opcodes
index 0e8fa06..bd120fd 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -29,6 +29,7 @@ arglut['crs2'] = (9,5)
 arglut['crs1'] = (14,10)
 arglut['crds'] = (15,13)
 arglut['crs2s'] = (15,13)
+arglut['crs2bs'] = (7,5)
 arglut['crs1s'] = (12,10)
 arglut['cimm6'] = (15,10)
 arglut['cimm10'] = (14,5)