[opcodes] fixed tex table for ish,ishw types

3 files changed, 130 insertions, 143 deletions

diff --git a/inst.v b/inst.v
index f2ce252..6e768aa 100644
--- a/inst.v
+++ b/inst.v
@@ -14,9 +14,9 @@
 `define ANDI       32'b1110100_?????_?????_100_????????????
 `define ORI        32'b1110100_?????_?????_101_????????????
 `define XORI       32'b1110100_?????_?????_110_????????????
-`define SLLI       32'b1110100_?????_?????_110000010_??????
-`define SRLI       32'b1110100_?????_?????_110000100_??????
-`define SRAI       32'b1110100_?????_?????_110000110_??????
+`define SLLI       32'b1110100_?????_?????_111000001_??????
+`define SRLI       32'b1110100_?????_?????_111000010_??????
+`define SRAI       32'b1110100_?????_?????_111000011_??????
 `define ADD        32'b1110101_?????_?????_0000000000_?????
 `define SUB        32'b1110101_?????_?????_0000000001_?????
 `define SLT        32'b1110101_?????_?????_0000000010_?????
@@ -36,9 +36,9 @@
 `define REM        32'b1110101_?????_?????_0010000110_?????
 `define REMU       32'b1110101_?????_?????_0010000111_?????
 `define ADDIW      32'b1110110_?????_?????_000_????????????
-`define SLLIW      32'b1110110_?????_?????_110000010_0_?????
-`define SRLIW      32'b1110110_?????_?????_110000100_0_?????
-`define SRAIW      32'b1110110_?????_?????_110000110_0_?????
+`define SLLIW      32'b1110110_?????_?????_111000001_0_?????
+`define SRLIW      32'b1110110_?????_?????_111000010_0_?????
+`define SRAIW      32'b1110110_?????_?????_111000011_0_?????
 `define ADDW       32'b1110111_?????_?????_0000000000_?????
 `define SUBW       32'b1110111_?????_?????_0000000001_?????
 `define SLLW       32'b1110111_?????_?????_1110000010_?????
diff --git a/instr-table.tex b/instr-table.tex
index e7b0bcd..14f731f 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -11,9 +11,9 @@
 \hspace*{0.5in} &
 \hspace*{0.5in} &
 \hspace*{0.3in} &
+\hspace*{0.2in} &
+\hspace*{0.4in} &
 \hspace*{0.1in} &
-\hspace*{0.1in} &
-\hspace*{0.5in} &
 \hspace*{0.5in} \\
                       &
 \instbitrange{31}{27} &
@@ -21,9 +21,9 @@
 \instbitrange{24}{20} &
 \instbitrange{19}{15} &
 \instbitrange{14}{12} &
-\instbit{11} &
-\instbit{10} &
-\instbitrange{9}{5} &
+\instbitrange{11}{10} &
+\instbitrange{9}{6} &
+\instbit{5} &
 \instbitrange{4}{0} \\
 \cline{2-10}
 &
@@ -44,26 +44,25 @@
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{2}{c|}{funct4} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rc} & RSH-type \\
+\multicolumn{3}{c|}{funct9} &
+\multicolumn{2}{c|}{shamt} & ISH-type \\
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
 \multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{3}{c|}{funct5} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{rc} & R4-type \\
+\multicolumn{4}{c|}{funct10} &
+\multicolumn{1}{c|}{rc} & R-type \\
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
 \multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{4}{c|}{funct10} &
-\multicolumn{1}{c|}{rc} & R-type \\
+\multicolumn{2}{c|}{funct5} &
+\multicolumn{2}{c|}{rd} &
+\multicolumn{1}{c|}{rc} & R4-type \\
 \cline{2-10}
   
 
@@ -465,9 +464,9 @@
 \hspace*{0.5in} &
 \hspace*{0.5in} &
 \hspace*{0.3in} &
+\hspace*{0.2in} &
+\hspace*{0.4in} &
 \hspace*{0.1in} &
-\hspace*{0.1in} &
-\hspace*{0.5in} &
 \hspace*{0.5in} \\
                       &
 \instbitrange{31}{27} &
@@ -475,9 +474,9 @@
 \instbitrange{24}{20} &
 \instbitrange{19}{15} &
 \instbitrange{14}{12} &
-\instbit{11} &
-\instbit{10} &
-\instbitrange{9}{5} &
+\instbitrange{11}{10} &
+\instbitrange{9}{6} &
+\instbit{5} &
 \instbitrange{4}{0} \\
 \cline{2-10}
 &
@@ -498,26 +497,25 @@
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{2}{c|}{funct4} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rc} & RSH-type \\
+\multicolumn{3}{c|}{funct9} &
+\multicolumn{2}{c|}{shamt} & ISH-type \\
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
 \multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{3}{c|}{funct5} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{rc} & R4-type \\
+\multicolumn{4}{c|}{funct10} &
+\multicolumn{1}{c|}{rc} & R-type \\
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
 \multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{4}{c|}{funct10} &
-\multicolumn{1}{c|}{rc} & R-type \\
+\multicolumn{2}{c|}{funct5} &
+\multicolumn{2}{c|}{rd} &
+\multicolumn{1}{c|}{rc} & R4-type \\
 \cline{2-10}
   
 
@@ -591,31 +589,28 @@
 
 &
 \multicolumn{2}{|c|}{1110100} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{xa} &
 \multicolumn{1}{c|}{xb} &
-\multicolumn{2}{c|}{1110} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{00000} & SLLI xa,xb,shamt \\
+\multicolumn{3}{c|}{111000001} &
+\multicolumn{2}{c|}{shamt} & SLLI xa,xb,shamt \\
 \cline{2-10}
   
 
 &
 \multicolumn{2}{|c|}{1110100} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{xa} &
 \multicolumn{1}{c|}{xb} &
-\multicolumn{2}{c|}{1110} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{00000} & SRLI xa,xb,shamt \\
+\multicolumn{3}{c|}{111000010} &
+\multicolumn{2}{c|}{shamt} & SRLI xa,xb,shamt \\
 \cline{2-10}
   
 
 &
 \multicolumn{2}{|c|}{1110100} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{xa} &
 \multicolumn{1}{c|}{xb} &
-\multicolumn{2}{c|}{1110} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{00000} & SRAI xa,xb,shamt \\
+\multicolumn{3}{c|}{111000011} &
+\multicolumn{2}{c|}{shamt} & SRAI xa,xb,shamt \\
 \cline{2-10}
   
 
@@ -799,34 +794,31 @@
 
 &
 \multicolumn{2}{|c|}{1110110} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{xa} &
 \multicolumn{1}{c|}{xb} &
-\multicolumn{2}{c|}{1110} &
+\multicolumn{3}{c|}{111000001} &
 \multicolumn{1}{c|}{0} &
-\multicolumn{1}{c|}{shamtw} &
-\multicolumn{1}{c|}{00000} & SLLIW xa,xb,shamtw \\
+\multicolumn{1}{c|}{shamtw} & SLLIW xa,xb,shamtw \\
 \cline{2-10}
   
 
 &
 \multicolumn{2}{|c|}{1110110} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{xa} &
 \multicolumn{1}{c|}{xb} &
-\multicolumn{2}{c|}{1110} &
+\multicolumn{3}{c|}{111000010} &
 \multicolumn{1}{c|}{0} &
-\multicolumn{1}{c|}{shamtw} &
-\multicolumn{1}{c|}{00000} & SRLIW xa,xb,shamtw \\
+\multicolumn{1}{c|}{shamtw} & SRLIW xa,xb,shamtw \\
 \cline{2-10}
   
 
 &
 \multicolumn{2}{|c|}{1110110} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{xa} &
 \multicolumn{1}{c|}{xb} &
-\multicolumn{2}{c|}{1110} &
+\multicolumn{3}{c|}{111000011} &
 \multicolumn{1}{c|}{0} &
-\multicolumn{1}{c|}{shamtw} &
-\multicolumn{1}{c|}{00000} & SRAIW xa,xb,shamtw \\
+\multicolumn{1}{c|}{shamtw} & SRAIW xa,xb,shamtw \\
 \cline{2-10}
   
 
@@ -958,9 +950,9 @@
 \hspace*{0.5in} &
 \hspace*{0.5in} &
 \hspace*{0.3in} &
+\hspace*{0.2in} &
+\hspace*{0.4in} &
 \hspace*{0.1in} &
-\hspace*{0.1in} &
-\hspace*{0.5in} &
 \hspace*{0.5in} \\
                       &
 \instbitrange{31}{27} &
@@ -968,9 +960,9 @@
 \instbitrange{24}{20} &
 \instbitrange{19}{15} &
 \instbitrange{14}{12} &
-\instbit{11} &
-\instbit{10} &
-\instbitrange{9}{5} &
+\instbitrange{11}{10} &
+\instbitrange{9}{6} &
+\instbit{5} &
 \instbitrange{4}{0} \\
 \cline{2-10}
 &
@@ -991,26 +983,25 @@
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{2}{c|}{funct4} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rc} & RSH-type \\
+\multicolumn{3}{c|}{funct9} &
+\multicolumn{2}{c|}{shamt} & ISH-type \\
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
 \multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{3}{c|}{funct5} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{rc} & R4-type \\
+\multicolumn{4}{c|}{funct10} &
+\multicolumn{1}{c|}{rc} & R-type \\
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
 \multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{4}{c|}{funct10} &
-\multicolumn{1}{c|}{rc} & R-type \\
+\multicolumn{2}{c|}{funct5} &
+\multicolumn{2}{c|}{rd} &
+\multicolumn{1}{c|}{rc} & R4-type \\
 \cline{2-10}
   
 
@@ -1212,8 +1203,8 @@
 \multicolumn{2}{|c|}{1101011} &
 \multicolumn{1}{c|}{fa} &
 \multicolumn{1}{c|}{fb} &
-\multicolumn{3}{c|}{00000} &
-\multicolumn{1}{c|}{fd} &
+\multicolumn{2}{c|}{00000} &
+\multicolumn{2}{c|}{fd} &
 \multicolumn{1}{c|}{fc} & MADD.S fc,fb,fa,fd \\
 \cline{2-10}
   
@@ -1222,8 +1213,8 @@
 \multicolumn{2}{|c|}{1101011} &
 \multicolumn{1}{c|}{fa} &
 \multicolumn{1}{c|}{fb} &
-\multicolumn{3}{c|}{00001} &
-\multicolumn{1}{c|}{fd} &
+\multicolumn{2}{c|}{00001} &
+\multicolumn{2}{c|}{fd} &
 \multicolumn{1}{c|}{fc} & MSUB.S fc,fb,fa,fd \\
 \cline{2-10}
   
@@ -1232,8 +1223,8 @@
 \multicolumn{2}{|c|}{1101011} &
 \multicolumn{1}{c|}{fa} &
 \multicolumn{1}{c|}{fb} &
-\multicolumn{3}{c|}{00010} &
-\multicolumn{1}{c|}{fd} &
+\multicolumn{2}{c|}{00010} &
+\multicolumn{2}{c|}{fd} &
 \multicolumn{1}{c|}{fc} & NMADD.S fc,fb,fa,fd \\
 \cline{2-10}
   
@@ -1242,8 +1233,8 @@
 \multicolumn{2}{|c|}{1101011} &
 \multicolumn{1}{c|}{fa} &
 \multicolumn{1}{c|}{fb} &
-\multicolumn{3}{c|}{00011} &
-\multicolumn{1}{c|}{fd} &
+\multicolumn{2}{c|}{00011} &
+\multicolumn{2}{c|}{fd} &
 \multicolumn{1}{c|}{fc} & NMSUB.S fc,fb,fa,fd \\
 \cline{2-10}
   
@@ -1252,8 +1243,8 @@
 \multicolumn{2}{|c|}{1101011} &
 \multicolumn{1}{c|}{fa} &
 \multicolumn{1}{c|}{fb} &
-\multicolumn{3}{c|}{11000} &
-\multicolumn{1}{c|}{fd} &
+\multicolumn{2}{c|}{11000} &
+\multicolumn{2}{c|}{fd} &
 \multicolumn{1}{c|}{fc} & MADD.D fc,fb,fa,fd \\
 \cline{2-10}
   
@@ -1262,8 +1253,8 @@
 \multicolumn{2}{|c|}{1101011} &
 \multicolumn{1}{c|}{fa} &
 \multicolumn{1}{c|}{fb} &
-\multicolumn{3}{c|}{11001} &
-\multicolumn{1}{c|}{fd} &
+\multicolumn{2}{c|}{11001} &
+\multicolumn{2}{c|}{fd} &
 \multicolumn{1}{c|}{fc} & MSUB.D fc,fb,fa,fd \\
 \cline{2-10}
   
@@ -1272,8 +1263,8 @@
 \multicolumn{2}{|c|}{1101011} &
 \multicolumn{1}{c|}{fa} &
 \multicolumn{1}{c|}{fb} &
-\multicolumn{3}{c|}{11010} &
-\multicolumn{1}{c|}{fd} &
+\multicolumn{2}{c|}{11010} &
+\multicolumn{2}{c|}{fd} &
 \multicolumn{1}{c|}{fc} & NMADD.D fc,fb,fa,fd \\
 \cline{2-10}
   
@@ -1282,8 +1273,8 @@
 \multicolumn{2}{|c|}{1101011} &
 \multicolumn{1}{c|}{fa} &
 \multicolumn{1}{c|}{fb} &
-\multicolumn{3}{c|}{11011} &
-\multicolumn{1}{c|}{fd} &
+\multicolumn{2}{c|}{11011} &
+\multicolumn{2}{c|}{fd} &
 \multicolumn{1}{c|}{fc} & NMSUB.D fc,fb,fa,fd \\
 \cline{2-10}
   
@@ -1369,9 +1360,9 @@
 \hspace*{0.5in} &
 \hspace*{0.5in} &
 \hspace*{0.3in} &
+\hspace*{0.2in} &
+\hspace*{0.4in} &
 \hspace*{0.1in} &
-\hspace*{0.1in} &
-\hspace*{0.5in} &
 \hspace*{0.5in} \\
                       &
 \instbitrange{31}{27} &
@@ -1379,9 +1370,9 @@
 \instbitrange{24}{20} &
 \instbitrange{19}{15} &
 \instbitrange{14}{12} &
-\instbit{11} &
-\instbit{10} &
-\instbitrange{9}{5} &
+\instbitrange{11}{10} &
+\instbitrange{9}{6} &
+\instbit{5} &
 \instbitrange{4}{0} \\
 \cline{2-10}
 &
@@ -1402,26 +1393,25 @@
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{2}{c|}{funct4} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rc} & RSH-type \\
+\multicolumn{3}{c|}{funct9} &
+\multicolumn{2}{c|}{shamt} & ISH-type \\
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
 \multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{3}{c|}{funct5} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{rc} & R4-type \\
+\multicolumn{4}{c|}{funct10} &
+\multicolumn{1}{c|}{rc} & R-type \\
 \cline{2-10}
 &
 \multicolumn{2}{|c|}{opcode} &
 \multicolumn{1}{c|}{ra} &
 \multicolumn{1}{c|}{rb} &
-\multicolumn{4}{c|}{funct10} &
-\multicolumn{1}{c|}{rc} & R-type \\
+\multicolumn{2}{c|}{funct5} &
+\multicolumn{2}{c|}{rd} &
+\multicolumn{1}{c|}{rc} & R4-type \\
 \cline{2-10}
   
 
diff --git a/parse-opcodes b/parse-opcodes
index 8b9b660..1151e1f 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -214,19 +214,18 @@ def print_ish_type(name,match,arguments):
   print """
 &
 \\multicolumn{2}{|c|}{%s} &
-\\multicolumn{1}{c|}{00000} &
 \\multicolumn{1}{c|}{%s} &
-\\multicolumn{2}{c|}{%s} &
-\\multicolumn{2}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} & %s \\\\
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} & %s \\\\
 \\cline{2-10}
   """ % \
   ( \
     binary(yank(match,25,7),7), \
+    str_arg('xa','',match,arguments), \
     str_arg('xb','',match,arguments), \
-    binary(yank(match,11,4),4), \
+    binary(yank(match,6,9),9), \
     str_arg('shamt','',match,arguments), \
-    str_arg('xc','',match,arguments), \
     str_inst(name,arguments) \
   )
 
@@ -234,60 +233,59 @@ def print_ishw_type(name,match,arguments):
   print """
 &
 \\multicolumn{2}{|c|}{%s} &
-\\multicolumn{1}{c|}{00000} &
 \\multicolumn{1}{c|}{%s} &
-\\multicolumn{2}{c|}{%s} &
-\\multicolumn{1}{c|}{0} &
 \\multicolumn{1}{c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
+\\multicolumn{1}{c|}{0} &
 \\multicolumn{1}{c|}{%s} & %s \\\\
 \\cline{2-10}
   """ % \
   ( \
     binary(yank(match,25,7),7), \
+    str_arg('xa','',match,arguments), \
     str_arg('xb','',match,arguments), \
-    binary(yank(match,11,4),4), \
+    binary(yank(match,6,9),9), \
     str_arg('shamtw','',match,arguments), \
-    str_arg('xc','',match,arguments), \
     str_inst(name,arguments) \
   )
 
-def print_r4_type(name,match,arguments):
+def print_r_type(name,match,arguments):
   print """
 &
 \\multicolumn{2}{|c|}{%s} &
 \\multicolumn{1}{c|}{%s} &
 \\multicolumn{1}{c|}{%s} &
-\\multicolumn{3}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
+\\multicolumn{4}{c|}{%s} &
 \\multicolumn{1}{c|}{%s} & %s \\\\
 \\cline{2-10}
   """ % \
   ( \
     binary(yank(match,25,7),7), \
-    str_arg('fa','',match,arguments), \
-    str_arg('fb','',match,arguments), \
-    binary(yank(match,10,5),5), \
-    str_arg('fd','',match,arguments), \
-    str_arg('fc','',match,arguments), \
+    str_arg('xa','fa',match,arguments), \
+    str_arg('xb','fb',match,arguments), \
+    binary(yank(match,5,10),10), \
+    str_arg('xc','fc',match,arguments), \
     str_inst(name,arguments) \
   )
 
-def print_r_type(name,match,arguments):
+def print_r4_type(name,match,arguments):
   print """
 &
 \\multicolumn{2}{|c|}{%s} &
 \\multicolumn{1}{c|}{%s} &
 \\multicolumn{1}{c|}{%s} &
-\\multicolumn{4}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
 \\multicolumn{1}{c|}{%s} & %s \\\\
 \\cline{2-10}
   """ % \
   ( \
     binary(yank(match,25,7),7), \
-    str_arg('xa','fa',match,arguments), \
-    str_arg('xb','fb',match,arguments), \
-    binary(yank(match,5,10),10), \
-    str_arg('xc','fc',match,arguments), \
+    str_arg('fa','',match,arguments), \
+    str_arg('fb','',match,arguments), \
+    binary(yank(match,10,5),5), \
+    str_arg('fd','',match,arguments), \
+    str_arg('fc','',match,arguments), \
     str_inst(name,arguments) \
   )
 
@@ -305,9 +303,9 @@ def print_header():
 \\hspace*{0.5in} &
 \\hspace*{0.5in} &
 \\hspace*{0.3in} &
+\\hspace*{0.2in} &
+\\hspace*{0.4in} &
 \\hspace*{0.1in} &
-\\hspace*{0.1in} &
-\\hspace*{0.5in} &
 \\hspace*{0.5in} \\\\
                       &
 \\instbitrange{31}{27} &
@@ -315,9 +313,9 @@ def print_header():
 \\instbitrange{24}{20} &
 \\instbitrange{19}{15} &
 \\instbitrange{14}{12} &
-\\instbit{11} &
-\\instbit{10} &
-\\instbitrange{9}{5} &
+\\instbitrange{11}{10} &
+\\instbitrange{9}{6} &
+\\instbit{5} &
 \\instbitrange{4}{0} \\\\
 \\cline{2-10}
 &
@@ -338,26 +336,25 @@ def print_header():
 \\cline{2-10}
 &
 \\multicolumn{2}{|c|}{opcode} &
-\\multicolumn{1}{c|}{00000} &
+\\multicolumn{1}{c|}{ra} &
 \\multicolumn{1}{c|}{rb} &
-\\multicolumn{2}{c|}{funct4} &
-\\multicolumn{2}{c|}{shamt} &
-\\multicolumn{1}{c|}{rc} & RSH-type \\\\
+\\multicolumn{3}{c|}{funct9} &
+\\multicolumn{2}{c|}{shamt} & ISH-type \\\\
 \\cline{2-10}
 &
 \\multicolumn{2}{|c|}{opcode} &
 \\multicolumn{1}{c|}{ra} &
 \\multicolumn{1}{c|}{rb} &
-\\multicolumn{3}{c|}{funct5} &
-\\multicolumn{1}{c|}{rd} &
-\\multicolumn{1}{c|}{rc} & R4-type \\\\
+\\multicolumn{4}{c|}{funct10} &
+\\multicolumn{1}{c|}{rc} & R-type \\\\
 \\cline{2-10}
 &
 \\multicolumn{2}{|c|}{opcode} &
 \\multicolumn{1}{c|}{ra} &
 \\multicolumn{1}{c|}{rb} &
-\\multicolumn{4}{c|}{funct10} &
-\\multicolumn{1}{c|}{rc} & R-type \\\\
+\\multicolumn{2}{c|}{funct5} &
+\\multicolumn{2}{c|}{rd} &
+\\multicolumn{1}{c|}{rc} & R4-type \\\\
 \\cline{2-10}
   """
 
@@ -504,7 +501,7 @@ def print_verilog_ish_type(name,match,arguments):
     binary(yank(match,25,7),7), \
     str_verilog_arg('xa','',match,arguments), \
     str_verilog_arg('xb','',match,arguments), \
-    binary(yank(match,5,9),9), \
+    binary(yank(match,6,9),9), \
     str_verilog_arg('shamt','',match,arguments) \
   )
 
@@ -515,7 +512,7 @@ def print_verilog_ishw_type(name,match,arguments):
     binary(yank(match,25,7),7), \
     str_verilog_arg('xa','',match,arguments), \
     str_verilog_arg('xb','',match,arguments), \
-    binary(yank(match,5,9),9), \
+    binary(yank(match,6,9),9), \
     str_verilog_arg('shamtw','',match,arguments) \
   )