diff options
| author |  Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-25 22:51:24 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-25 22:51:24 -0800 |
| commit | c5440481e6feaa917f247a85e8e30275b360d398 (patch) | |
| tree | cf0cc14a931e3b43f14c95b848dc984e77106cfa | |
| parent | 478ff61a9244f13dbb4c605a32d428e46f0b4d5b (diff) | |
[opcodes,pk,sim,xcc] great renumbering of 2011, part deux
| -rw-r--r-- | inst.v | 288 | ||||
| -rw-r--r-- | instr-table.tex | 122 | ||||
| -rw-r--r-- | opcodes | 357 | ||||
| -rwxr-xr-x | parse-opcodes | 45 |
4 files changed, 402 insertions, 410 deletions
@@ -1,152 +1,150 @@ `define UNIMP 32'b00000000000000000000000000000000 -`define J 32'b?????????????????????????_1100000 -`define JAL 32'b?????????????????????????_1100001 -`define JALR_C 32'b?????_?????_????????????_000_1100010 -`define JALR_R 32'b?????_?????_????????????_001_1100010 -`define JALR_J 32'b?????_?????_????????????_010_1100010 +`define J 32'b?????????????????????????_1100111 +`define JAL 32'b?????????????????????????_1101111 +`define JALR_C 32'b?????_?????_????????????_000_1101011 +`define JALR_R 32'b?????_?????_????????????_001_1101011 +`define JALR_J 32'b?????_?????_????????????_010_1101011 `define BEQ 32'b?????_?????_?????_???????_000_1100011 `define BNE 32'b?????_?????_?????_???????_001_1100011 `define BLT 32'b?????_?????_?????_???????_100_1100011 `define BGE 32'b?????_?????_?????_???????_101_1100011 `define BLTU 32'b?????_?????_?????_???????_110_1100011 `define BGEU 32'b?????_?????_?????_???????_111_1100011 -`define LUI 32'b?????_????????????????????_1110001 -`define ADDI 32'b?????_?????_????????????_000_1110100 -`define SLTI 32'b?????_?????_????????????_010_1110100 -`define SLTIU 32'b?????_?????_????????????_011_1110100 -`define ANDI 32'b?????_?????_????????????_100_1110100 -`define ORI 32'b?????_?????_????????????_101_1110100 -`define XORI 32'b?????_?????_????????????_110_1110100 -`define SLLI 32'b?????_?????_??????_000001_111_1110100 -`define SRLI 32'b?????_?????_??????_000010_111_1110100 -`define SRAI 32'b?????_?????_??????_000011_111_1110100 -`define ADD 32'b?????_?????_?????_0000000000_1110101 -`define SUB 32'b?????_?????_?????_0000001000_1110101 -`define SLT 32'b?????_?????_?????_0000010000_1110101 -`define SLTU 32'b?????_?????_?????_0000011000_1110101 -`define AND 32'b?????_?????_?????_0000100000_1110101 -`define OR 32'b?????_?????_?????_0000101000_1110101 -`define XOR 32'b?????_?????_?????_0000110000_1110101 -`define SLL 32'b?????_?????_?????_0000001111_1110101 -`define SRL 32'b?????_?????_?????_0000010111_1110101 -`define SRA 32'b?????_?????_?????_0000011111_1110101 -`define MUL 32'b?????_?????_?????_0000000001_1110101 -`define MULH 32'b?????_?????_?????_0000010001_1110101 -`define MULHU 32'b?????_?????_?????_0000011001_1110101 -`define DIV 32'b?????_?????_?????_0000100001_1110101 -`define DIVU 32'b?????_?????_?????_0000101001_1110101 -`define REM 32'b?????_?????_?????_0000110001_1110101 -`define REMU 32'b?????_?????_?????_0000111001_1110101 -`define ADDIW 32'b?????_?????_????????????_000_1110110 -`define SLLIW 32'b?????_?????_0_?????_000001_111_1110110 -`define SRLIW 32'b?????_?????_0_?????_000010_111_1110110 -`define SRAIW 32'b?????_?????_0_?????_000011_111_1110110 -`define ADDW 32'b?????_?????_?????_0000000000_1110111 -`define SUBW 32'b?????_?????_?????_0000001000_1110111 -`define SLLW 32'b?????_?????_?????_0000001111_1110111 -`define SRLW 32'b?????_?????_?????_0000010111_1110111 -`define SRAW 32'b?????_?????_?????_0000011111_1110111 -`define MULW 32'b?????_?????_?????_0000000001_1110111 -`define DIVW 32'b?????_?????_?????_0000100001_1110111 -`define DIVUW 32'b?????_?????_?????_0000101001_1110111 -`define REMW 32'b?????_?????_?????_0000110001_1110111 -`define REMUW 32'b?????_?????_?????_0000111001_1110111 -`define L_B 32'b?????_?????_????????????_000_1111000 -`define L_H 32'b?????_?????_????????????_001_1111000 -`define L_W 32'b?????_?????_????????????_010_1111000 -`define L_D 32'b?????_?????_????????????_011_1111000 -`define L_BU 32'b?????_?????_????????????_100_1111000 -`define L_HU 32'b?????_?????_????????????_101_1111000 -`define L_WU 32'b?????_?????_????????????_110_1111000 -`define SYNCI 32'b00000_?????_????????????_111_1111000 -`define S_B 32'b?????_?????_?????_???????_000_1111001 -`define S_H 32'b?????_?????_?????_???????_001_1111001 -`define S_W 32'b?????_?????_?????_???????_010_1111001 -`define S_D 32'b?????_?????_?????_???????_011_1111001 -`define AMOADD_W 32'b?????_?????_?????_0000000010_1111010 -`define AMOSWAP_W 32'b?????_?????_?????_0000001010_1111010 -`define AMOAND_W 32'b?????_?????_?????_0000010010_1111010 -`define AMOOR_W 32'b?????_?????_?????_0000011010_1111010 -`define AMOMIN_W 32'b?????_?????_?????_0000100010_1111010 -`define AMOMAX_W 32'b?????_?????_?????_0000101010_1111010 -`define AMOMINU_W 32'b?????_?????_?????_0000110010_1111010 -`define AMOMAXU_W 32'b?????_?????_?????_0000111010_1111010 -`define AMOADD_D 32'b?????_?????_?????_0000000011_1111010 -`define AMOSWAP_D 32'b?????_?????_?????_0000001011_1111010 -`define AMOAND_D 32'b?????_?????_?????_0000010011_1111010 -`define AMOOR_D 32'b?????_?????_?????_0000011011_1111010 -`define AMOMIN_D 32'b?????_?????_?????_0000100011_1111010 -`define AMOMAX_D 32'b?????_?????_?????_0000101011_1111010 -`define AMOMINU_D 32'b?????_?????_?????_0000110011_1111010 -`define AMOMAXU_D 32'b?????_?????_?????_0000111011_1111010 -`define RDNPC 32'b?????_00000_00000_0000000000_1111011 -`define MFCR 32'b?????_00000_?????_0000000001_1111011 -`define MTCR 32'b00000_?????_?????_0000001001_1111011 -`define SYNC 32'b00000_00000_00000_0000000010_1111011 -`define SYSCALL 32'b00000_00000_????????????_011_1111011 -`define EI 32'b?????_00000_00000_0000000000_1101011 -`define DI 32'b?????_00000_00000_0000001000_1101011 -`define MFPCR 32'b?????_00000_?????_0000000001_1101011 -`define MTPCR 32'b00000_?????_?????_0000001001_1101011 -`define ERET 32'b00000_00000_00000_0000000010_1101011 -`define FADD_S 32'b?????_?????_?????_00000_???_00_1101010 -`define FSUB_S 32'b?????_?????_?????_00001_???_00_1101010 -`define FMUL_S 32'b?????_?????_?????_00010_???_00_1101010 -`define FDIV_S 32'b?????_?????_?????_00011_???_00_1101010 -`define FSQRT_S 32'b?????_?????_00000_00100_???_00_1101010 -`define FSINJ_S 32'b?????_?????_?????_0010100000_1101010 -`define FSINJN_S 32'b?????_?????_?????_0011000000_1101010 -`define FSMUL_S 32'b?????_?????_?????_0011100000_1101010 -`define FADD_D 32'b?????_?????_?????_00000_???_11_1101010 -`define FSUB_D 32'b?????_?????_?????_00001_???_11_1101010 -`define FMUL_D 32'b?????_?????_?????_00010_???_11_1101010 -`define FDIV_D 32'b?????_?????_?????_00011_???_11_1101010 -`define FSQRT_D 32'b?????_?????_00000_00100_???_11_1101010 -`define FSINJ_D 32'b?????_?????_?????_0010100011_1101010 -`define FSINJN_D 32'b?????_?????_?????_0011000011_1101010 -`define FSMUL_D 32'b?????_?????_?????_0011100011_1101010 -`define FCVT_L_S 32'b?????_?????_00000_01000_???_00_1101010 -`define FCVTU_L_S 32'b?????_?????_00000_01001_???_00_1101010 -`define FCVT_W_S 32'b?????_?????_00000_01010_???_00_1101010 -`define FCVTU_W_S 32'b?????_?????_00000_01011_???_00_1101010 -`define FCVT_L_D 32'b?????_?????_00000_01000_???_11_1101010 -`define FCVTU_L_D 32'b?????_?????_00000_01001_???_11_1101010 -`define FCVT_W_D 32'b?????_?????_00000_01010_???_11_1101010 -`define FCVTU_W_D 32'b?????_?????_00000_01011_???_11_1101010 -`define FCVT_S_L 32'b?????_?????_00000_01100_???_00_1101010 -`define FCVTU_S_L 32'b?????_?????_00000_01101_???_00_1101010 -`define FCVT_S_W 32'b?????_?????_00000_01110_???_00_1101010 -`define FCVTU_S_W 32'b?????_?????_00000_01111_???_00_1101010 -`define FCVT_D_L 32'b?????_?????_00000_01100_???_11_1101010 -`define FCVTU_D_L 32'b?????_?????_00000_01101_???_11_1101010 -`define FCVT_D_W 32'b?????_?????_00000_0111000011_1101010 -`define FCVTU_D_W 32'b?????_?????_00000_0111100011_1101010 -`define FCVT_S_D 32'b?????_?????_00000_10011_???_00_1101010 -`define FCVT_D_S 32'b?????_?????_00000_1000000011_1101010 -`define FC_EQ_S 32'b?????_?????_?????_1010100000_1101010 -`define FC_LT_S 32'b?????_?????_?????_1011000000_1101010 -`define FC_LE_S 32'b?????_?????_?????_1011100000_1101010 -`define FC_EQ_D 32'b?????_?????_?????_1010100011_1101010 -`define FC_LT_D 32'b?????_?????_?????_1011000011_1101010 -`define FC_LE_D 32'b?????_?????_?????_1011100011_1101010 -`define MFF_S 32'b?????_00000_?????_1100001000_1101010 -`define MFF_D 32'b?????_00000_?????_1100001011_1101010 -`define MFFL_D 32'b?????_00000_?????_1100101011_1101010 -`define MFFH_D 32'b?????_00000_?????_1101001011_1101010 -`define MTF_S 32'b?????_?????_00000_1110001000_1101010 -`define MTF_D 32'b?????_?????_00000_1110001011_1101010 -`define MTFLH_D 32'b?????_?????_?????_1110001111_1101010 -`define LF_W 32'b?????_?????_????????????_010_1101000 -`define LF_D 32'b?????_?????_????????????_011_1101000 -`define SF_W 32'b?????_?????_?????_???????_010_1101001 -`define SF_D 32'b?????_?????_?????_???????_011_1101001 -`define FSEL_S 32'b?????_?????_?????_0000000000_1100111 -`define FSEL_D 32'b?????_?????_?????_0000000011_1100111 -`define FMADD_S 32'b?????_?????_?????_?????_???_00_1101100 -`define FMSUB_S 32'b?????_?????_?????_?????_???_00_1101101 -`define FNMSUB_S 32'b?????_?????_?????_?????_???_00_1101110 -`define FNMADD_S 32'b?????_?????_?????_?????_???_00_1101111 -`define FMADD_D 32'b?????_?????_?????_?????_???_11_1101100 -`define FMSUB_D 32'b?????_?????_?????_?????_???_11_1101101 -`define FNMSUB_D 32'b?????_?????_?????_?????_???_11_1101110 -`define FNMADD_D 32'b?????_?????_?????_?????_???_11_1101111 +`define LUI 32'b?????_????????????????????_0110111 +`define ADDI 32'b?????_?????_????????????_000_0010011 +`define SLLI 32'b?????_?????_??????_000000_001_0010011 +`define SLTI 32'b?????_?????_????????????_010_0010011 +`define SLTIU 32'b?????_?????_????????????_011_0010011 +`define XORI 32'b?????_?????_????????????_100_0010011 +`define SRLI 32'b?????_?????_??????_000000_101_0010011 +`define SRAI 32'b?????_?????_??????_000000_101_0010011 +`define ORI 32'b?????_?????_????????????_110_0010011 +`define ANDI 32'b?????_?????_????????????_111_0010011 +`define ADD 32'b?????_?????_?????_0000000000_0110011 +`define SUB 32'b?????_?????_?????_1000000000_0110011 +`define SLL 32'b?????_?????_?????_0000000001_0110011 +`define SLT 32'b?????_?????_?????_0000000010_0110011 +`define SLTU 32'b?????_?????_?????_0000000011_0110011 +`define XOR 32'b?????_?????_?????_0000000100_0110011 +`define SRL 32'b?????_?????_?????_0000000101_0110011 +`define SRA 32'b?????_?????_?????_1000000101_0110011 +`define OR 32'b?????_?????_?????_0000000110_0110011 +`define AND 32'b?????_?????_?????_0000000111_0110011 +`define MUL 32'b?????_?????_?????_0000001000_0110011 +`define MULH 32'b?????_?????_?????_0000001010_0110011 +`define MULHU 32'b?????_?????_?????_0000001011_0110011 +`define DIV 32'b?????_?????_?????_0000001100_0110011 +`define DIVU 32'b?????_?????_?????_0000001101_0110011 +`define REM 32'b?????_?????_?????_0000001110_0110011 +`define REMU 32'b?????_?????_?????_0000001111_0110011 +`define ADDIW 32'b?????_?????_????????????_000_0011011 +`define SLLIW 32'b?????_?????_0_?????_000000_001_0011011 +`define SRLIW 32'b?????_?????_0_?????_000000_101_0011011 +`define SRAIW 32'b?????_?????_0_?????_000000_101_0011011 +`define ADDW 32'b?????_?????_?????_0000000000_0111011 +`define SUBW 32'b?????_?????_?????_1000000000_0111011 +`define SLLW 32'b?????_?????_?????_0000000001_0111011 +`define SRLW 32'b?????_?????_?????_0000000101_0111011 +`define SRAW 32'b?????_?????_?????_1000000101_0111011 +`define MULW 32'b?????_?????_?????_0000001000_0111011 +`define DIVW 32'b?????_?????_?????_0000001100_0111011 +`define DIVUW 32'b?????_?????_?????_0000001101_0111011 +`define REMW 32'b?????_?????_?????_0000001110_0111011 +`define REMUW 32'b?????_?????_?????_0000001111_0111011 +`define L_B 32'b?????_?????_????????????_000_0000011 +`define L_H 32'b?????_?????_????????????_001_0000011 +`define L_W 32'b?????_?????_????????????_010_0000011 +`define L_D 32'b?????_?????_????????????_011_0000011 +`define L_BU 32'b?????_?????_????????????_100_0000011 +`define L_HU 32'b?????_?????_????????????_101_0000011 +`define L_WU 32'b?????_?????_????????????_110_0000011 +`define SYNCI 32'b00000_?????_????????????_111_0000011 +`define S_B 32'b?????_?????_?????_???????_000_0100011 +`define S_H 32'b?????_?????_?????_???????_001_0100011 +`define S_W 32'b?????_?????_?????_???????_010_0100011 +`define S_D 32'b?????_?????_?????_???????_011_0100011 +`define AMOADD_W 32'b?????_?????_?????_00000_000_10_1000011 +`define AMOSWAP_W 32'b?????_?????_?????_00000_010_10_1000011 +`define AMOAND_W 32'b?????_?????_?????_00000_100_10_1000011 +`define AMOOR_W 32'b?????_?????_?????_00000_110_10_1000011 +`define AMOMIN_W 32'b?????_?????_?????_00001_000_10_1000011 +`define AMOMAX_W 32'b?????_?????_?????_00001_010_10_1000011 +`define AMOMINU_W 32'b?????_?????_?????_00001_100_10_1000011 +`define AMOMAXU_W 32'b?????_?????_?????_00001_110_10_1000011 +`define AMOADD_D 32'b?????_?????_?????_00000_000_11_1000011 +`define AMOSWAP_D 32'b?????_?????_?????_00000_010_11_1000011 +`define AMOAND_D 32'b?????_?????_?????_00000_100_11_1000011 +`define AMOOR_D 32'b?????_?????_?????_00000_110_11_1000011 +`define AMOMIN_D 32'b?????_?????_?????_00001_000_11_1000011 +`define AMOMAX_D 32'b?????_?????_?????_00001_010_11_1000011 +`define AMOMINU_D 32'b?????_?????_?????_00001_100_11_1000011 +`define AMOMAXU_D 32'b?????_?????_?????_00001_110_11_1000011 +`define RDNPC 32'b?????_00000_00000_0000000000_0010111 +`define MFCR 32'b?????_00000_?????_0000000001_0010111 +`define MTCR 32'b00000_?????_?????_0000001001_0010111 +`define SYNC 32'b00000_00000_00000_0000000010_0010111 +`define SYSCALL 32'b00000_00000_????????????_011_0010111 +`define EI 32'b?????_00000_00000_0000000000_1111111 +`define DI 32'b?????_00000_00000_0000001000_1111111 +`define MFPCR 32'b?????_00000_?????_0000000001_1111111 +`define MTPCR 32'b00000_?????_?????_0000001001_1111111 +`define ERET 32'b00000_00000_00000_0000000010_1111111 +`define FADD_S 32'b?????_?????_?????_00000_???_00_1010011 +`define FSUB_S 32'b?????_?????_?????_00001_???_00_1010011 +`define FMUL_S 32'b?????_?????_?????_00010_???_00_1010011 +`define FDIV_S 32'b?????_?????_?????_00011_???_00_1010011 +`define FSQRT_S 32'b?????_?????_00000_00100_???_00_1010011 +`define FSINJ_S 32'b?????_?????_?????_0010100000_1010011 +`define FSINJN_S 32'b?????_?????_?????_0011000000_1010011 +`define FSMUL_S 32'b?????_?????_?????_0011100000_1010011 +`define FADD_D 32'b?????_?????_?????_00000_???_01_1010011 +`define FSUB_D 32'b?????_?????_?????_00001_???_01_1010011 +`define FMUL_D 32'b?????_?????_?????_00010_???_01_1010011 +`define FDIV_D 32'b?????_?????_?????_00011_???_01_1010011 +`define FSQRT_D 32'b?????_?????_00000_00100_???_01_1010011 +`define FSINJ_D 32'b?????_?????_?????_0010100001_1010011 +`define FSINJN_D 32'b?????_?????_?????_0011000001_1010011 +`define FSMUL_D 32'b?????_?????_?????_0011100001_1010011 +`define FCVT_L_S 32'b?????_?????_00000_01000_???_00_1010011 +`define FCVTU_L_S 32'b?????_?????_00000_01001_???_00_1010011 +`define FCVT_W_S 32'b?????_?????_00000_01010_???_00_1010011 +`define FCVTU_W_S 32'b?????_?????_00000_01011_???_00_1010011 +`define FCVT_L_D 32'b?????_?????_00000_01000_???_01_1010011 +`define FCVTU_L_D 32'b?????_?????_00000_01001_???_01_1010011 +`define FCVT_W_D 32'b?????_?????_00000_01010_???_01_1010011 +`define FCVTU_W_D 32'b?????_?????_00000_01011_???_01_1010011 +`define FCVT_S_L 32'b?????_?????_00000_01100_???_00_1010011 +`define FCVTU_S_L 32'b?????_?????_00000_01101_???_00_1010011 +`define FCVT_S_W 32'b?????_?????_00000_01110_???_00_1010011 +`define FCVTU_S_W 32'b?????_?????_00000_01111_???_00_1010011 +`define FCVT_D_L 32'b?????_?????_00000_01100_???_01_1010011 +`define FCVTU_D_L 32'b?????_?????_00000_01101_???_01_1010011 +`define FCVT_D_W 32'b?????_?????_00000_0111000001_1010011 +`define FCVTU_D_W 32'b?????_?????_00000_0111100001_1010011 +`define FCVT_S_D 32'b?????_?????_00000_10001_???_00_1010011 +`define FCVT_D_S 32'b?????_?????_00000_1000000001_1010011 +`define FC_EQ_S 32'b?????_?????_?????_1010100000_1010011 +`define FC_LT_S 32'b?????_?????_?????_1011000000_1010011 +`define FC_LE_S 32'b?????_?????_?????_1011100000_1010011 +`define FC_EQ_D 32'b?????_?????_?????_1010100001_1010011 +`define FC_LT_D 32'b?????_?????_?????_1011000001_1010011 +`define FC_LE_D 32'b?????_?????_?????_1011100001_1010011 +`define MFF_S 32'b?????_00000_?????_1100001000_1010011 +`define MFF_D 32'b?????_00000_?????_1100001001_1010011 +`define MFFL_D 32'b?????_00000_?????_1100101001_1010011 +`define MFFH_D 32'b?????_00000_?????_1101001001_1010011 +`define MTF_S 32'b?????_?????_00000_1110001000_1010011 +`define MTF_D 32'b?????_?????_00000_1110001001_1010011 +`define MTFLH_D 32'b?????_?????_?????_1110001101_1010011 +`define LF_W 32'b?????_?????_????????????_010_0000111 +`define LF_D 32'b?????_?????_????????????_011_0000111 +`define SF_W 32'b?????_?????_?????_???????_010_0100111 +`define SF_D 32'b?????_?????_?????_???????_011_0100111 +`define FMADD_S 32'b?????_?????_?????_?????_???_00_1000011 +`define FMSUB_S 32'b?????_?????_?????_?????_???_00_1000111 +`define FNMSUB_S 32'b?????_?????_?????_?????_???_00_1001011 +`define FNMADD_S 32'b?????_?????_?????_?????_???_00_1001111 +`define FMADD_D 32'b?????_?????_?????_?????_???_01_1000011 +`define FMSUB_D 32'b?????_?????_?????_?????_???_01_1000111 +`define FNMSUB_D 32'b?????_?????_?????_?????_???_01_1001011 +`define FNMADD_D 32'b?????_?????_?????_?????_???_01_1001111 diff --git a/instr-table.tex b/instr-table.tex index cb1092e..04d9bdc 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -197,9 +197,10 @@ & \multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{2}{c|}{000000} & +\multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLTI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SLLI rd,rs1,shamt \\ \cline{2-10} @@ -208,7 +209,7 @@ \multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLTIU rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SLTI rd,rs1,imm12 \\ \cline{2-10} @@ -217,7 +218,7 @@ \multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & ANDI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SLTIU rd,rs1,imm12 \\ \cline{2-10} @@ -226,46 +227,45 @@ \multicolumn{2}{c|}{000} & \multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & ORI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & XORI rd,rs1,imm12 \\ \cline{2-10} & \multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & -\multicolumn{4}{c|}{imm12} & +\multicolumn{2}{c|}{000000} & +\multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & XORI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rd} & SRLI rd,rs1,shamt \\ \cline{2-10} & \multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & -\multicolumn{2}{c|}{000000} & +\multicolumn{2}{c|}{000001} & \multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLLI rd,rs1,shamt \\ +\multicolumn{1}{c|}{rd} & SRAI rd,rs1,shamt \\ \cline{2-10} & \multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & -\multicolumn{2}{c|}{000000} & -\multicolumn{2}{c|}{shamt} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRLI rd,rs1,shamt \\ +\multicolumn{1}{c|}{rd} & ORI rd,rs1,imm12 \\ \cline{2-10} & \multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & -\multicolumn{2}{c|}{000000} & -\multicolumn{2}{c|}{shamt} & +\multicolumn{4}{c|}{imm12} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRAI rd,rs1,shamt \\ +\multicolumn{1}{c|}{rd} & ANDI rd,rs1,imm12 \\ \cline{2-10} @@ -280,7 +280,7 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SUB rd,rs1,rs2 \\ @@ -292,7 +292,7 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLT rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & SLL rd,rs1,rs2 \\ \cline{2-10} @@ -301,7 +301,7 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLTU rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & SLT rd,rs1,rs2 \\ \cline{2-10} @@ -310,7 +310,7 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & AND rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & SLTU rd,rs1,rs2 \\ \cline{2-10} @@ -319,7 +319,7 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & OR rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & XOR rd,rs1,rs2 \\ \cline{2-10} @@ -328,16 +328,16 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & XOR rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & SRL rd,rs1,rs2 \\ \cline{2-10} & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SLL rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & SRA rd,rs1,rs2 \\ \cline{2-10} @@ -346,7 +346,7 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRL rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & OR rd,rs1,rs2 \\ \cline{2-10} @@ -355,7 +355,7 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & SRA rd,rs1,rs2 \\ +\multicolumn{1}{c|}{rd} & AND rd,rs1,rs2 \\ \cline{2-10} @@ -456,7 +456,7 @@ & \multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & -\multicolumn{2}{c|}{000000} & +\multicolumn{2}{c|}{000001} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{shamtw} & \multicolumn{1}{c|}{rd} & @@ -475,7 +475,7 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SUBW rd,rs1,rs2 \\ @@ -502,7 +502,7 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{5}{c|}{0000000010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & SRAW rd,rs1,rs2 \\ @@ -668,7 +668,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOADD.W rd,rs1,rs2 \\ @@ -677,7 +678,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOSWAP.W rd,rs1,rs2 \\ @@ -686,7 +688,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOAND.W rd,rs1,rs2 \\ @@ -695,7 +698,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOOR.W rd,rs1,rs2 \\ @@ -704,7 +708,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOMIN.W rd,rs1,rs2 \\ @@ -713,7 +718,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOMAX.W rd,rs1,rs2 \\ @@ -722,7 +728,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOMINU.W rd,rs1,rs2 \\ @@ -731,7 +738,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOMAXU.W rd,rs1,rs2 \\ @@ -740,7 +748,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOADD.D rd,rs1,rs2 \\ @@ -749,7 +758,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOSWAP.D rd,rs1,rs2 \\ @@ -758,7 +768,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOAND.D rd,rs1,rs2 \\ @@ -767,7 +778,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOOR.D rd,rs1,rs2 \\ @@ -776,7 +788,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOMIN.D rd,rs1,rs2 \\ @@ -785,7 +798,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOMAX.D rd,rs1,rs2 \\ @@ -794,7 +808,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOMINU.D rd,rs1,rs2 \\ @@ -803,7 +818,8 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & +\multicolumn{3}{c|}{00000} & +\multicolumn{2}{c|}{00001} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rd} & AMOMAXU.D rd,rs1,rs2 \\ @@ -1413,24 +1429,6 @@ & \multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & FSEL.S rd,rs1,rs2,rs3 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{0000000} & -\multicolumn{5}{c|}{0000000000} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rd} & FSEL.D rd,rs1,rs2,rs3 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{0000000} & \multicolumn{1}{c|}{00} & \multicolumn{2}{c|}{rm} & \multicolumn{2}{c|}{rs3} & @@ -2,195 +2,192 @@ # <instruction name> <opcode> <args> # # <opcode> is given by specifying one or more range/value pairs: -# highbit..lowbit=value (e.g. 6..0=0x45 9..7=0x0) +# highbit..lowbit=value (e.g. 6..2=0x45 9..7=0x0) # # <args> is one of xa,xb,xc,fa,fb,fc,fd,imm,imm20,imm27,shamt,shamtw unimp 31..0=0 -j imm25 6..0=0x60 -jal imm25 6..0=0x61 - -jalr.c rd rs1 imm12 9..7=0 6..0=0x62 -jalr.r rd rs1 imm12 9..7=1 6..0=0x62 -jalr.j rd rs1 imm12 9..7=2 6..0=0x62 - -beq imm12hi rs1 rs2 imm12lo 9..7=0 6..0=0x63 -bne imm12hi rs1 rs2 imm12lo 9..7=1 6..0=0x63 -blt imm12hi rs1 rs2 imm12lo 9..7=4 6..0=0x63 -bge imm12hi rs1 rs2 imm12lo 9..7=5 6..0=0x63 -bltu imm12hi rs1 rs2 imm12lo 9..7=6 6..0=0x63 -bgeu imm12hi rs1 rs2 imm12lo 9..7=7 6..0=0x63 - -lui rd imm20 6..0=0x71 - -addi rd rs1 imm12 9..7=0 6..0=0x74 -slti rd rs1 imm12 9..7=2 6..0=0x74 -sltiu rd rs1 imm12 9..7=3 6..0=0x74 -andi rd rs1 imm12 9..7=4 6..0=0x74 -ori rd rs1 imm12 9..7=5 6..0=0x74 -xori rd rs1 imm12 9..7=6 6..0=0x74 -slli rd rs1 shamt 15..10=1 9..7=7 6..0=0x74 -srli rd rs1 shamt 15..10=2 9..7=7 6..0=0x74 -srai rd rs1 shamt 15..10=3 9..7=7 6..0=0x74 - -add rd rs1 rs2 16..10=0 9..7=0 6..0=0x75 -sub rd rs1 rs2 16..10=1 9..7=0 6..0=0x75 -slt rd rs1 rs2 16..10=2 9..7=0 6..0=0x75 -sltu rd rs1 rs2 16..10=3 9..7=0 6..0=0x75 -and rd rs1 rs2 16..10=4 9..7=0 6..0=0x75 -or rd rs1 rs2 16..10=5 9..7=0 6..0=0x75 -xor rd rs1 rs2 16..10=6 9..7=0 6..0=0x75 -sll rd rs1 rs2 16=0 15..10=1 9..7=7 6..0=0x75 -srl rd rs1 rs2 16=0 15..10=2 9..7=7 6..0=0x75 -sra rd rs1 rs2 16=0 15..10=3 9..7=7 6..0=0x75 - -mul rd rs1 rs2 16..10=0 9..7=1 6..0=0x75 -mulh rd rs1 rs2 16..10=2 9..7=1 6..0=0x75 -mulhu rd rs1 rs2 16..10=3 9..7=1 6..0=0x75 -div rd rs1 rs2 16..10=4 9..7=1 6..0=0x75 -divu rd rs1 rs2 16..10=5 9..7=1 6..0=0x75 -rem rd rs1 rs2 16..10=6 9..7=1 6..0=0x75 -remu rd rs1 rs2 16..10=7 9..7=1 6..0=0x75 - -addiw rd rs1 imm12 9..7=0 6..0=0x76 -slliw rd rs1 21=0 shamtw 15..10=1 9..7=7 6..0=0x76 -srliw rd rs1 21=0 shamtw 15..10=2 9..7=7 6..0=0x76 -sraiw rd rs1 21=0 shamtw 15..10=3 9..7=7 6..0=0x76 - -addw rd rs1 rs2 16..10=0 9..7=0 6..0=0x77 -subw rd rs1 rs2 16..10=1 9..7=0 6..0=0x77 -sllw rd rs1 rs2 16=0 15..10=1 9..7=7 6..0=0x77 -srlw rd rs1 rs2 16=0 15..10=2 9..7=7 6..0=0x77 -sraw rd rs1 rs2 16=0 15..10=3 9..7=7 6..0=0x77 - -mulw rd rs1 rs2 16..10=0 9..7=1 6..0=0x77 -divw rd rs1 rs2 16..10=4 9..7=1 6..0=0x77 -divuw rd rs1 rs2 16..10=5 9..7=1 6..0=0x77 -remw rd rs1 rs2 16..10=6 9..7=1 6..0=0x77 -remuw rd rs1 rs2 16..10=7 9..7=1 6..0=0x77 - -l.b rd rs1 imm12 9..7=0 6..0=0x78 -l.h rd rs1 imm12 9..7=1 6..0=0x78 -l.w rd rs1 imm12 9..7=2 6..0=0x78 -l.d rd rs1 imm12 9..7=3 6..0=0x78 -l.bu rd rs1 imm12 9..7=4 6..0=0x78 -l.hu rd rs1 imm12 9..7=5 6..0=0x78 -l.wu rd rs1 imm12 9..7=6 6..0=0x78 -synci 31..27=0 rs1 imm12 9..7=7 6..0=0x78 +j imm25 6..2=0x19 1..0=3 +jal imm25 6..2=0x1B 1..0=3 + +jalr.c rd rs1 imm12 9..7=0 6..2=0x1A 1..0=3 +jalr.r rd rs1 imm12 9..7=1 6..2=0x1A 1..0=3 +jalr.j rd rs1 imm12 9..7=2 6..2=0x1A 1..0=3 + +beq imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x18 1..0=3 +bne imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x18 1..0=3 +blt imm12hi rs1 rs2 imm12lo 9..7=4 6..2=0x18 1..0=3 +bge imm12hi rs1 rs2 imm12lo 9..7=5 6..2=0x18 1..0=3 +bltu imm12hi rs1 rs2 imm12lo 9..7=6 6..2=0x18 1..0=3 +bgeu imm12hi rs1 rs2 imm12lo 9..7=7 6..2=0x18 1..0=3 + +lui rd imm20 6..2=0x0D 1..0=3 + +addi rd rs1 imm12 9..7=0 6..2=0x04 1..0=3 +slli rd rs1 21..17=0 16=0 shamt 9..7=1 6..2=0x04 1..0=3 +slti rd rs1 imm12 9..7=2 6..2=0x04 1..0=3 +sltiu rd rs1 imm12 9..7=3 6..2=0x04 1..0=3 +xori rd rs1 imm12 9..7=4 6..2=0x04 1..0=3 +srli rd rs1 21..17=0 16=0 shamt 9..7=5 6..2=0x04 1..0=3 +srai rd rs1 21..17=0 16=1 shamt 9..7=5 6..2=0x04 1..0=3 +ori rd rs1 imm12 9..7=6 6..2=0x04 1..0=3 +andi rd rs1 imm12 9..7=7 6..2=0x04 1..0=3 + +add rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0C 1..0=3 +sub rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0C 1..0=3 +sll rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0C 1..0=3 +slt rd rs1 rs2 16=0 15..10=0 9..7=2 6..2=0x0C 1..0=3 +sltu rd rs1 rs2 16=0 15..10=0 9..7=3 6..2=0x0C 1..0=3 +xor rd rs1 rs2 16=0 15..10=0 9..7=4 6..2=0x0C 1..0=3 +srl rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0C 1..0=3 +sra rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0C 1..0=3 +or rd rs1 rs2 16=0 15..10=0 9..7=6 6..2=0x0C 1..0=3 +and rd rs1 rs2 16=0 15..10=0 9..7=7 6..2=0x0C 1..0=3 + +mul rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0C 1..0=3 +mulh rd rs1 rs2 16=0 15..10=1 9..7=2 6..2=0x0C 1..0=3 +mulhu rd rs1 rs2 16=0 15..10=1 9..7=3 6..2=0x0C 1..0=3 +div rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0C 1..0=3 +divu rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0C 1..0=3 +rem rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0C 1..0=3 +remu rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0C 1..0=3 + +addiw rd rs1 imm12 9..7=0 6..2=0x06 1..0=3 +slliw rd rs1 21..17=0 16=0 15=0 shamtw 9..7=1 6..2=0x06 1..0=3 +srliw rd rs1 21..17=0 16=0 15=0 shamtw 9..7=5 6..2=0x06 1..0=3 +sraiw rd rs1 21..17=0 16=1 15=0 shamtw 9..7=5 6..2=0x06 1..0=3 + +addw rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0E 1..0=3 +subw rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0E 1..0=3 +sllw rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0E 1..0=3 +srlw rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0E 1..0=3 +sraw rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0E 1..0=3 + +mulw rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0E 1..0=3 +divw rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0E 1..0=3 +divuw rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0E 1..0=3 +remw rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0E 1..0=3 +remuw rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0E 1..0=3 + +l.b rd rs1 imm12 9..7=0 6..2=0x00 1..0=3 +l.h rd rs1 imm12 9..7=1 6..2=0x00 1..0=3 +l.w rd rs1 imm12 9..7=2 6..2=0x00 1..0=3 +l.d rd rs1 imm12 9..7=3 6..2=0x00 1..0=3 +l.bu rd rs1 imm12 9..7=4 6..2=0x00 1..0=3 +l.hu rd rs1 imm12 9..7=5 6..2=0x00 1..0=3 +l.wu rd rs1 imm12 9..7=6 6..2=0x00 1..0=3 +synci 31..27=0 rs1 imm12 9..7=7 6..2=0x00 1..0=3 # NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c # and elfxx-mips.c to detect them. this is a hack to handle the split immed. -# just open up those files and search for MATCH_SW; should be obvious. -s.b imm12hi rs1 rs2 imm12lo 9..7=0 6..0=0x79 -s.h imm12hi rs1 rs2 imm12lo 9..7=1 6..0=0x79 -s.w imm12hi rs1 rs2 imm12lo 9..7=2 6..0=0x79 -s.d imm12hi rs1 rs2 imm12lo 9..7=3 6..0=0x79 - -amoadd.w rd rs1 rs2 16..10=0 9..7=2 6..0=0x7A -amoswap.w rd rs1 rs2 16..10=1 9..7=2 6..0=0x7A -amoand.w rd rs1 rs2 16..10=2 9..7=2 6..0=0x7A -amoor.w rd rs1 rs2 16..10=3 9..7=2 6..0=0x7A -amomin.w rd rs1 rs2 16..10=4 9..7=2 6..0=0x7A -amomax.w rd rs1 rs2 16..10=5 9..7=2 6..0=0x7A -amominu.w rd rs1 rs2 16..10=6 9..7=2 6..0=0x7A -amomaxu.w rd rs1 rs2 16..10=7 9..7=2 6..0=0x7A +# just open up those files and search for MATCH_S_W; should be obvious. +s.b imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x08 1..0=3 +s.h imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x08 1..0=3 +s.w imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x08 1..0=3 +s.d imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x08 1..0=3 + +amoadd.w rd rs1 rs2 16..10=0 9..7=2 6..2=0x10 1..0=3 +amoswap.w rd rs1 rs2 16..10=1 9..7=2 6..2=0x10 1..0=3 +amoand.w rd rs1 rs2 16..10=2 9..7=2 6..2=0x10 1..0=3 +amoor.w rd rs1 rs2 16..10=3 9..7=2 6..2=0x10 1..0=3 +amomin.w rd rs1 rs2 16..10=4 9..7=2 6..2=0x10 1..0=3 +amomax.w rd rs1 rs2 16..10=5 9..7=2 6..2=0x10 1..0=3 +amominu.w rd rs1 rs2 16..10=6 9..7=2 6..2=0x10 1..0=3 +amomaxu.w rd rs1 rs2 16..10=7 9..7=2 6..2=0x10 1..0=3 -amoadd.d rd rs1 rs2 16..10=0 9..7=3 6..0=0x7A -amoswap.d rd rs1 rs2 16..10=1 9..7=3 6..0=0x7A -amoand.d rd rs1 rs2 16..10=2 9..7=3 6..0=0x7A -amoor.d rd rs1 rs2 16..10=3 9..7=3 6..0=0x7A -amomin.d rd rs1 rs2 16..10=4 9..7=3 6..0=0x7A -amomax.d rd rs1 rs2 16..10=5 9..7=3 6..0=0x7A -amominu.d rd rs1 rs2 16..10=6 9..7=3 6..0=0x7A -amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..0=0x7A - -rdnpc rd 26..17=0 16..10=0 9..7=0 6..0=0x7B -mfcr rd 26..22=0 rs2 16..10=0 9..7=1 6..0=0x7B -mtcr 31..27=0 rs1 rs2 16..10=1 9..7=1 6..0=0x7B -sync 31..17=0 16..10=0 9..7=2 6..0=0x7B -syscall 31..22=0 imm12 9..7=3 6..0=0x7B - -ei rd 26..17=0 16..10=0 9..7=0 6..0=0x6B -di rd 26..17=0 16..10=1 9..7=0 6..0=0x6B -mfpcr rd 26..22=0 rs2 16..10=0 9..7=1 6..0=0x6B -mtpcr 31..27=0 rs1 rs2 16..10=1 9..7=1 6..0=0x6B -eret 31..17=0 16..10=0 9..7=2 6..0=0x6B +amoadd.d rd rs1 rs2 16..10=0 9..7=3 6..2=0x10 1..0=3 +amoswap.d rd rs1 rs2 16..10=1 9..7=3 6..2=0x10 1..0=3 +amoand.d rd rs1 rs2 16..10=2 9..7=3 6..2=0x10 1..0=3 +amoor.d rd rs1 rs2 16..10=3 9..7=3 6..2=0x10 1..0=3 +amomin.d rd rs1 rs2 16..10=4 9..7=3 6..2=0x10 1..0=3 +amomax.d rd rs1 rs2 16..10=5 9..7=3 6..2=0x10 1..0=3 +amominu.d rd rs1 rs2 16..10=6 9..7=3 6..2=0x10 1..0=3 +amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x10 1..0=3 + +rdnpc rd 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x05 1..0=3 +mfcr rd 26..22=0 rs2 16..10=0 9..7=1 6..2=0x05 1..0=3 +mtcr 31..27=0 rs1 rs2 16..10=1 9..7=1 6..2=0x05 1..0=3 +sync 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x05 1..0=3 +syscall 31..27=0 26..22=0 imm12 9..7=3 6..2=0x05 1..0=3 + +ei rd 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x1F 1..0=3 +di rd 26..22=0 21..17=0 16..10=1 9..7=0 6..2=0x1F 1..0=3 +mfpcr rd 26..22=0 rs2 16..10=0 9..7=1 6..2=0x1F 1..0=3 +mtpcr 31..27=0 rs1 rs2 16..10=1 9..7=1 6..2=0x1F 1..0=3 +eret 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1F 1..0=3 # 0x7C-0x7F are reserved for >32b instructions -fadd.s rd rs1 rs2 16..12=0 rm 8..7=0 6..0=0x6A -fsub.s rd rs1 rs2 16..12=1 rm 8..7=0 6..0=0x6A -fmul.s rd rs1 rs2 16..12=2 rm 8..7=0 6..0=0x6A -fdiv.s rd rs1 rs2 16..12=3 rm 8..7=0 6..0=0x6A -fsqrt.s rd rs1 21..17=0 16..12=4 rm 8..7=0 6..0=0x6A -fsinj.s rd rs1 rs2 16..12=5 11..9=0 8..7=0 6..0=0x6A -fsinjn.s rd rs1 rs2 16..12=6 11..9=0 8..7=0 6..0=0x6A -fsmul.s rd rs1 rs2 16..12=7 11..9=0 8..7=0 6..0=0x6A - -fadd.d rd rs1 rs2 16..12=0x0 rm 8..7=3 6..0=0x6A -fsub.d rd rs1 rs2 16..12=0x1 rm 8..7=3 6..0=0x6A -fmul.d rd rs1 rs2 16..12=0x2 rm 8..7=3 6..0=0x6A -fdiv.d rd rs1 rs2 16..12=0x3 rm 8..7=3 6..0=0x6A -fsqrt.d rd rs1 21..17=0 16..12=0x4 rm 8..7=3 6..0=0x6A -fsinj.d rd rs1 rs2 16..12=0x5 11..9=0 8..7=3 6..0=0x6A -fsinjn.d rd rs1 rs2 16..12=0x6 11..9=0 8..7=3 6..0=0x6A -fsmul.d rd rs1 rs2 16..12=0x7 11..9=0 8..7=3 6..0=0x6A - -fcvt.l.s rd rs1 21..17=0 16..12=0x8 rm 8..7=0 6..0=0x6A -fcvtu.l.s rd rs1 21..17=0 16..12=0x9 rm 8..7=0 6..0=0x6A -fcvt.w.s rd rs1 21..17=0 16..12=0xA rm 8..7=0 6..0=0x6A -fcvtu.w.s rd rs1 21..17=0 16..12=0xB rm 8..7=0 6..0=0x6A - -fcvt.l.d rd rs1 21..17=0 16..12=0x8 rm 8..7=3 6..0=0x6A -fcvtu.l.d rd rs1 21..17=0 16..12=0x9 rm 8..7=3 6..0=0x6A -fcvt.w.d rd rs1 21..17=0 16..12=0xA rm 8..7=3 6..0=0x6A -fcvtu.w.d rd rs1 21..17=0 16..12=0xB rm 8..7=3 6..0=0x6A - -fcvt.s.l rd rs1 21..17=0 16..12=0xC rm 8..7=0 6..0=0x6A -fcvtu.s.l rd rs1 21..17=0 16..12=0xD rm 8..7=0 6..0=0x6A -fcvt.s.w rd rs1 21..17=0 16..12=0xE rm 8..7=0 6..0=0x6A -fcvtu.s.w rd rs1 21..17=0 16..12=0xF rm 8..7=0 6..0=0x6A - -fcvt.d.l rd rs1 21..17=0 16..12=0xC rm 8..7=3 6..0=0x6A -fcvtu.d.l rd rs1 21..17=0 16..12=0xD rm 8..7=3 6..0=0x6A -fcvt.d.w rd rs1 21..17=0 16..12=0xE 11..9=0 8..7=3 6..0=0x6A -fcvtu.d.w rd rs1 21..17=0 16..12=0xF 11..9=0 8..7=3 6..0=0x6A - -fcvt.s.d rd rs1 21..17=0 16..12=0x13 rm 8..7=0 6..0=0x6A -fcvt.d.s rd rs1 21..17=0 16..12=0x10 11..9=0 8..7=3 6..0=0x6A - -fc.eq.s rd rs1 rs2 16..12=0x15 11..9=0 8..7=0 6..0=0x6A -fc.lt.s rd rs1 rs2 16..12=0x16 11..9=0 8..7=0 6..0=0x6A -fc.le.s rd rs1 rs2 16..12=0x17 11..9=0 8..7=0 6..0=0x6A - -fc.eq.d rd rs1 rs2 16..12=0x15 11..9=0 8..7=3 6..0=0x6A -fc.lt.d rd rs1 rs2 16..12=0x16 11..9=0 8..7=3 6..0=0x6A -fc.le.d rd rs1 rs2 16..12=0x17 11..9=0 8..7=3 6..0=0x6A - -mff.s rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=0 6..0=0x6A -mff.d rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=3 6..0=0x6A -mffl.d rd 26..22=0 rs2 16..12=0x19 11..9=2 8..7=3 6..0=0x6A -mffh.d rd 26..22=0 rs2 16..12=0x1A 11..9=2 8..7=3 6..0=0x6A -mtf.s rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=0 6..0=0x6A -mtf.d rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=3 6..0=0x6A -mtflh.d rd rs1 rs2 16..12=0x1C 11..9=3 8..7=3 6..0=0x6A - -lf.w rd rs1 imm12 9..7=2 6..0=0x68 -lf.d rd rs1 imm12 9..7=3 6..0=0x68 - -sf.w imm12hi rs1 rs2 imm12lo 9..7=2 6..0=0x69 -sf.d imm12hi rs1 rs2 imm12lo 9..7=3 6..0=0x69 - -fsel.s rd rs1 rs2 rs3 11..9=0 8..7=0 6..0=0x67 -fsel.d rd rs1 rs2 rs3 11..9=0 8..7=3 6..0=0x67 - -fmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6C -fmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6D -fnmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6E -fnmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6F - -fmadd.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6C -fmsub.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6D -fnmsub.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6E -fnmadd.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6F +fadd.s rd rs1 rs2 16..12=0 rm 8..7=0 6..2=0x14 1..0=3 +fsub.s rd rs1 rs2 16..12=1 rm 8..7=0 6..2=0x14 1..0=3 +fmul.s rd rs1 rs2 16..12=2 rm 8..7=0 6..2=0x14 1..0=3 +fdiv.s rd rs1 rs2 16..12=3 rm 8..7=0 6..2=0x14 1..0=3 +fsqrt.s rd rs1 21..17=0 16..12=4 rm 8..7=0 6..2=0x14 1..0=3 +fsinj.s rd rs1 rs2 16..12=5 11..9=0 8..7=0 6..2=0x14 1..0=3 +fsinjn.s rd rs1 rs2 16..12=6 11..9=0 8..7=0 6..2=0x14 1..0=3 +fsmul.s rd rs1 rs2 16..12=7 11..9=0 8..7=0 6..2=0x14 1..0=3 + +fadd.d rd rs1 rs2 16..12=0x0 rm 8..7=1 6..2=0x14 1..0=3 +fsub.d rd rs1 rs2 16..12=0x1 rm 8..7=1 6..2=0x14 1..0=3 +fmul.d rd rs1 rs2 16..12=0x2 rm 8..7=1 6..2=0x14 1..0=3 +fdiv.d rd rs1 rs2 16..12=0x3 rm 8..7=1 6..2=0x14 1..0=3 +fsqrt.d rd rs1 21..17=0 16..12=0x4 rm 8..7=1 6..2=0x14 1..0=3 +fsinj.d rd rs1 rs2 16..12=0x5 11..9=0 8..7=1 6..2=0x14 1..0=3 +fsinjn.d rd rs1 rs2 16..12=0x6 11..9=0 8..7=1 6..2=0x14 1..0=3 +fsmul.d rd rs1 rs2 16..12=0x7 11..9=0 8..7=1 6..2=0x14 1..0=3 + +fcvt.l.s rd rs1 21..17=0 16..12=0x8 rm 8..7=0 6..2=0x14 1..0=3 +fcvtu.l.s rd rs1 21..17=0 16..12=0x9 rm 8..7=0 6..2=0x14 1..0=3 +fcvt.w.s rd rs1 21..17=0 16..12=0xA rm 8..7=0 6..2=0x14 1..0=3 +fcvtu.w.s rd rs1 21..17=0 16..12=0xB rm 8..7=0 6..2=0x14 1..0=3 + +fcvt.l.d rd rs1 21..17=0 16..12=0x8 rm 8..7=1 6..2=0x14 1..0=3 +fcvtu.l.d rd rs1 21..17=0 16..12=0x9 rm 8..7=1 6..2=0x14 1..0=3 +fcvt.w.d rd rs1 21..17=0 16..12=0xA rm 8..7=1 6..2=0x14 1..0=3 +fcvtu.w.d rd rs1 21..17=0 16..12=0xB rm 8..7=1 6..2=0x14 1..0=3 + +fcvt.s.l rd rs1 21..17=0 16..12=0xC rm 8..7=0 6..2=0x14 1..0=3 +fcvtu.s.l rd rs1 21..17=0 16..12=0xD rm 8..7=0 6..2=0x14 1..0=3 +fcvt.s.w rd rs1 21..17=0 16..12=0xE rm 8..7=0 6..2=0x14 1..0=3 +fcvtu.s.w rd rs1 21..17=0 16..12=0xF rm 8..7=0 6..2=0x14 1..0=3 + +fcvt.d.l rd rs1 21..17=0 16..12=0xC rm 8..7=1 6..2=0x14 1..0=3 +fcvtu.d.l rd rs1 21..17=0 16..12=0xD rm 8..7=1 6..2=0x14 1..0=3 +fcvt.d.w rd rs1 21..17=0 16..12=0xE 11..9=0 8..7=1 6..2=0x14 1..0=3 +fcvtu.d.w rd rs1 21..17=0 16..12=0xF 11..9=0 8..7=1 6..2=0x14 1..0=3 + +fcvt.s.d rd rs1 21..17=0 16..14=0x4 13..12=1 rm 8..7=0 6..2=0x14 1..0=3 +fcvt.d.s rd rs1 21..17=0 16..14=0x4 13..12=0 11..9=0 8..7=1 6..2=0x14 1..0=3 + +fc.eq.s rd rs1 rs2 16..12=0x15 11..9=0 8..7=0 6..2=0x14 1..0=3 +fc.lt.s rd rs1 rs2 16..12=0x16 11..9=0 8..7=0 6..2=0x14 1..0=3 +fc.le.s rd rs1 rs2 16..12=0x17 11..9=0 8..7=0 6..2=0x14 1..0=3 + +fc.eq.d rd rs1 rs2 16..12=0x15 11..9=0 8..7=1 6..2=0x14 1..0=3 +fc.lt.d rd rs1 rs2 16..12=0x16 11..9=0 8..7=1 6..2=0x14 1..0=3 +fc.le.d rd rs1 rs2 16..12=0x17 11..9=0 8..7=1 6..2=0x14 1..0=3 + +mff.s rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=0 6..2=0x14 1..0=3 +mff.d rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=1 6..2=0x14 1..0=3 +mffl.d rd 26..22=0 rs2 16..12=0x19 11..9=2 8..7=1 6..2=0x14 1..0=3 +mffh.d rd 26..22=0 rs2 16..12=0x1A 11..9=2 8..7=1 6..2=0x14 1..0=3 +mtf.s rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=0 6..2=0x14 1..0=3 +mtf.d rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=1 6..2=0x14 1..0=3 +mtflh.d rd rs1 rs2 16..12=0x1C 11..9=3 8..7=1 6..2=0x14 1..0=3 + +lf.w rd rs1 imm12 9..7=2 6..2=0x01 1..0=3 +lf.d rd rs1 imm12 9..7=3 6..2=0x01 1..0=3 + +sf.w imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x09 1..0=3 +sf.d imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x09 1..0=3 + +fmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x10 1..0=3 +fmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x11 1..0=3 +fnmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x12 1..0=3 +fnmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x13 1..0=3 + +fmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3 +fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 +fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 +fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index c8ab9e2..911c60e 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -21,33 +21,32 @@ arglut['imm20'] = (26,7) arglut['imm12'] = (21,10) arglut['imm12hi'] = (31,27) arglut['imm12lo'] = (16,10) -arglut['shamt'] = (21,16) -arglut['shamtw'] = (20,16) +arglut['shamt'] = (15,10) +arglut['shamtw'] = (14,10) typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,10=b typelut[0x00] = 0 -typelut[0x60] = 1 -typelut[0x61] = 1 -typelut[0x62] = 3 +typelut[0x67] = 1 +typelut[0x6F] = 1 +typelut[0x6B] = 3 typelut[0x63] = 10 -typelut[0x71] = 2 -typelut[0x74] = 3 -typelut[0x75] = 4 -typelut[0x76] = 3 -typelut[0x77] = 4 -typelut[0x78] = 3 -typelut[0x79] = 10 -typelut[0x7a] = 4 -typelut[0x7b] = 4 -typelut[0x67] = 4 -typelut[0x68] = 3 -typelut[0x69] = 10 -typelut[0x6a] = 4 -typelut[0x6b] = 4 -typelut[0x6c] = 5 -typelut[0x6d] = 5 -typelut[0x6e] = 5 -typelut[0x6f] = 5 +typelut[0x37] = 2 +typelut[0x13] = 3 +typelut[0x33] = 4 +typelut[0x1B] = 3 +typelut[0x3B] = 4 +typelut[0x03] = 3 +typelut[0x23] = 10 +typelut[0x27] = 4 +typelut[0x17] = 4 +typelut[0x07] = 3 +typelut[0x27] = 10 +typelut[0x53] = 4 +typelut[0x43] = 5 +typelut[0x47] = 5 +typelut[0x4B] = 5 +typelut[0x4F] = 5 +typelut[0x7F] = 4 def binary(n, digits=0): rep = bin(n)[2:] |