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Author
Age
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hwacha v3: inst format follows the new rocket accelerator extensions
Yunsup Lee
2013-08-07
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Rename MTFSR/MFFSR to FSSR/FRSR
Andrew Waterman
2013-08-06
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Add custom opcode space
Andrew Waterman
2013-08-06
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HW ignores upper bits of fence, but SW supplies 0
Andrew Waterman
2013-07-31
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Swap J and JALR encodings
Andrew Waterman
2013-07-31
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change supervisor encoding
Yunsup Lee
2013-07-26
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tweaks
Yunsup Lee
2013-07-26
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Factor out Hwacha/RVC and rename MFTX/MXTF to FMV
Andrew Waterman
2013-07-26
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Refactor parse-opcodes
Andrew Waterman
2013-07-25
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Remove JALR static hints
Andrew Waterman
2013-07-25
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Remove CFLUSH
Andrew Waterman
2013-07-23
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add auipc, lr, sc
Andrew Waterman
2013-04-17
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new supervisor mode
Andrew Waterman
2012-03-24
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change vector fence names/encoding
Andrew Waterman
2012-03-18
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clean up vector exception instructions
Yunsup Lee
2012-03-18
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add more instructions for vector exception handling
Yunsup Lee
2012-03-13
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add vvcfg,vtcfg
Yunsup Lee
2012-03-13
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opcodes cleanup
Yunsup Lee
2012-03-13
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slight change to vector supervisor instructions
Yunsup Lee
2012-03-10
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new instructions to handle vector exceptions
Yunsup Lee
2012-03-03
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temporary undoing of renaming
Andrew Waterman
2011-06-19
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Renamed packages
Andrew Waterman
2011-06-19
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[riscv-isa-run] code cleanup; added README
Andrew Waterman
2011-06-19
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[sim, opcodes] made sim more decoupled from opcodes
Andrew Waterman
2011-06-10
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[sim,opcodes] improved sim build and run performance
Andrew Waterman
2011-05-29
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[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)
Yunsup Lee
2011-05-18
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[opcodes,pk,sim,xcc] resolve a conflict
Yunsup Lee
2011-05-15
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[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts
Yunsup Lee
2011-05-15
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tweaked encoding of rdcycle & cousins
Andrew Waterman
2011-05-13
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[opcodes] reordered RVC instructions
Andrew Waterman
2011-05-06
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[xcc,sim,opcodes] added c.addiw
Andrew Waterman
2011-04-24
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[xcc,sim,opcodes] added more RVC instructions
Andrew Waterman
2011-04-24
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[xcc,sim,opcodes] added rvc conditional branches
Andrew Waterman
2011-04-18
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[xcc,pk,sim] added privileged cflush instruction
Andrew Waterman
2011-04-12
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[xcc,sim] rvc loads and stores
Andrew Waterman
2011-04-12
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[xcc,sim,opcodes] more rvc instructions and bug fixes
Andrew Waterman
2011-04-11
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[xcc, sim] added rvc insn c.li; misc fixes
Andrew Waterman
2011-04-09
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[xcc,pk,sim,opcodes] added first RVC instruction
Andrew Waterman
2011-04-09
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[pk,sim] fixed parse-opcodes bug
Andrew Waterman
2011-04-07
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was causing spurious illegal instruction traps
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[opcodes,pk,sim,xcc] fix utidx - add rd
Yunsup Lee
2011-04-06
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[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem ↵
Yunsup Lee
2011-04-05
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instructions
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[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)
Yunsup Lee
2011-04-04
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[opcodes,pk,sim,xcc] add vector mem instructions
Yunsup Lee
2011-04-04
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[opcodes,pk,sim,xcc] add stop,utidx instructions
Yunsup Lee
2011-04-04
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[opcodes,pk,sim,xcc] add fence instructions for vector unit
Yunsup Lee
2011-04-04
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[opcodes] fixed up instruction table
Andrew Waterman
2011-03-25
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[opcodes] minor opcode changes
Andrew Waterman
2011-03-25
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[sim,pk,xcc,opcodes] removed fminmag/fmaxmag
Andrew Waterman
2011-03-25
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[xcc,pk,opcodes,sim] updated encoding/insn names
Andrew Waterman
2011-03-25
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[xcc,opcodes,pk,sim] krste's re-renaming spree
Andrew Waterman
2011-02-15
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