diff options
| author |  Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-15 22:33:25 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-15 22:46:06 -0700 |
| commit | f866323c541a6f26ac58cbbded41ea5c9f2b6fa4 (patch) | |
| tree | f98292a8ea4a6b5fda4066476da5449cbf7369f2 | |
| parent | 05e0d24dc582a92eae1809451833d5c76335b81a (diff) | |
[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts
| -rw-r--r-- | inst.v | 147 | ||||
| -rw-r--r-- | instr-table.tex | 40 | ||||
| -rw-r--r-- | opcodes | 196 | ||||
| -rwxr-xr-x | parse-opcodes | 31 |
4 files changed, 251 insertions, 163 deletions
@@ -92,6 +92,10 @@ `define FENCE_G_CV 32'b?????_?????_????????????_111_0101111 `define STOP 32'b00000_00000_00000_0000000010_1110111 `define UTIDX 32'b?????_00000_00000_0000000011_1110111 +`define MOVZ 32'b?????_?????_?????_0000000100_1110111 +`define MOVN 32'b?????_?????_?????_0000000101_1110111 +`define FMOVZ 32'b?????_?????_?????_0000000110_1110111 +`define FMOVN 32'b?????_?????_?????_0000000111_1110111 `define EI 32'b?????_00000_00000_0000000000_1111011 `define DI 32'b?????_00000_00000_0000000001_1111011 `define MFPCR 32'b?????_00000_?????_0000000010_1111011 @@ -160,77 +164,78 @@ `define FMSUB_D 32'b?????_?????_?????_?????_???_01_1000111 `define FNMSUB_D 32'b?????_?????_?????_?????_???_01_1001011 `define FNMADD_D 32'b?????_?????_?????_?????_???_01_1001111 -`define LD_V 32'b?????_?????_00000_0000000011_0001011 -`define LW_V 32'b?????_?????_00000_0000000010_0001011 -`define LWU_V 32'b?????_?????_00000_0000000110_0001011 -`define LH_V 32'b?????_?????_00000_0000000001_0001011 -`define LHU_V 32'b?????_?????_00000_0000000101_0001011 -`define LB_V 32'b?????_?????_00000_0000000000_0001011 -`define LBU_V 32'b?????_?????_00000_0000000100_0001011 -`define SD_V 32'b?????_?????_00000_0000010011_0001011 -`define SW_V 32'b?????_?????_00000_0000010010_0001011 -`define SH_V 32'b?????_?????_00000_0000010001_0001011 -`define SB_V 32'b?????_?????_00000_0000010000_0001011 -`define FLD_V 32'b?????_?????_00000_0000001011_0001011 -`define FLW_V 32'b?????_?????_00000_0000001010_0001011 -`define FSD_V 32'b?????_?????_00000_0000011011_0001011 -`define FSW_V 32'b?????_?????_00000_0000011010_0001011 -`define LDST_V 32'b?????_?????_?????_0000100011_0001011 -`define LWST_V 32'b?????_?????_?????_0000100010_0001011 -`define LWUST_V 32'b?????_?????_?????_0000100110_0001011 -`define LHST_V 32'b?????_?????_?????_0000100001_0001011 -`define LHUST_V 32'b?????_?????_?????_0000100101_0001011 -`define LBST_V 32'b?????_?????_?????_0000100000_0001011 -`define LBUST_V 32'b?????_?????_?????_0000100100_0001011 -`define SDST_V 32'b?????_?????_?????_0000110011_0001011 -`define SWST_V 32'b?????_?????_?????_0000110010_0001011 -`define SHST_V 32'b?????_?????_?????_0000110001_0001011 -`define SBST_V 32'b?????_?????_?????_0000110000_0001011 -`define FLDST_V 32'b?????_?????_?????_0000101011_0001011 -`define FLWST_V 32'b?????_?????_?????_0000101010_0001011 -`define FSDST_V 32'b?????_?????_?????_0000111011_0001011 -`define FSWST_V 32'b?????_?????_?????_0000111010_0001011 -`define LDSEG_V 32'b?????_?????_?????_0001000011_0001011 -`define LWSEG_V 32'b?????_?????_?????_0001000010_0001011 -`define LWUSEG_V 32'b?????_?????_?????_0001000110_0001011 -`define LHSEG_V 32'b?????_?????_?????_0001000001_0001011 -`define LHUSEG_V 32'b?????_?????_?????_0001000101_0001011 -`define LBSEG_V 32'b?????_?????_?????_0001000000_0001011 -`define LBUSEG_V 32'b?????_?????_?????_0001000100_0001011 -`define SDSEG_V 32'b?????_?????_?????_0001010011_0001011 -`define SWSEG_V 32'b?????_?????_?????_0001010010_0001011 -`define SHSEG_V 32'b?????_?????_?????_0001010001_0001011 -`define SBSEG_V 32'b?????_?????_?????_0001010000_0001011 -`define FLDSEG_V 32'b?????_?????_?????_0001001011_0001011 -`define FLWSEG_V 32'b?????_?????_?????_0001001010_0001011 -`define FSDSEG_V 32'b?????_?????_?????_0001011011_0001011 -`define FSWSEG_V 32'b?????_?????_?????_0001011010_0001011 -`define LDSEGST_V 32'b?????_?????_?????_?????_000_11_0001111 -`define LWSEGST_V 32'b?????_?????_?????_?????_000_10_0001111 -`define LWUSEGST_V 32'b?????_?????_?????_?????_001_10_0001111 -`define LHSEGST_V 32'b?????_?????_?????_?????_000_01_0001111 -`define LHUSEGST_V 32'b?????_?????_?????_?????_001_01_0001111 -`define LBSEGST_V 32'b?????_?????_?????_?????_000_00_0001111 -`define LBUSEGST_V 32'b?????_?????_?????_?????_001_00_0001111 -`define SDSEGST_V 32'b?????_?????_?????_?????_100_11_0001111 -`define SWSEGST_V 32'b?????_?????_?????_?????_100_10_0001111 -`define SHSEGST_V 32'b?????_?????_?????_?????_100_01_0001111 -`define SBSEGST_V 32'b?????_?????_?????_?????_100_00_0001111 -`define FLDSEGST_V 32'b?????_?????_?????_?????_010_11_0001111 -`define FLWSEGST_V 32'b?????_?????_?????_?????_010_10_0001111 -`define FSDSEGST_V 32'b?????_?????_?????_?????_110_11_0001111 -`define FSWSEGST_V 32'b?????_?????_?????_?????_110_10_0001111 -`define MOV_VV 32'b?????_?????_00000_1000000000_0001011 -`define MOV_SV 32'b?????_?????_00000_1000000001_0001011 -`define MOV_SU 32'b?????_?????_?????_1000000010_0001011 -`define MOV_US 32'b?????_?????_?????_1000000011_0001011 -`define FMOV_VV 32'b?????_?????_00000_1100000000_0001011 -`define FMOV_SV 32'b?????_?????_00000_1100000001_0001011 -`define FMOV_SU 32'b?????_?????_?????_1100000010_0001011 -`define FMOV_US 32'b?????_?????_?????_1100000011_0001011 -`define VCFGIVL 32'b?????_?????_????????????_000_1110011 -`define SETVL 32'b?????_?????_000000000000_001_1110011 -`define VF 32'b00000_?????_????????????_010_1110011 +`define VLD 32'b?????_?????_00000_0000000011_0001011 +`define VLW 32'b?????_?????_00000_0000000010_0001011 +`define VLWU 32'b?????_?????_00000_0000000110_0001011 +`define VLH 32'b?????_?????_00000_0000000001_0001011 +`define VLHU 32'b?????_?????_00000_0000000101_0001011 +`define VLB 32'b?????_?????_00000_0000000000_0001011 +`define VLBU 32'b?????_?????_00000_0000000100_0001011 +`define VFLD 32'b?????_?????_00000_0000001011_0001011 +`define VFLW 32'b?????_?????_00000_0000001010_0001011 +`define VLSTD 32'b?????_?????_?????_0000100011_0001011 +`define VLSTW 32'b?????_?????_?????_0000100010_0001011 +`define VLSTWU 32'b?????_?????_?????_0000100110_0001011 +`define VLSTH 32'b?????_?????_?????_0000100001_0001011 +`define VLSTHU 32'b?????_?????_?????_0000100101_0001011 +`define VLSTB 32'b?????_?????_?????_0000100000_0001011 +`define VLSTBU 32'b?????_?????_?????_0000100100_0001011 +`define VFLSTD 32'b?????_?????_?????_0000101011_0001011 +`define VFLSTW 32'b?????_?????_?????_0000101010_0001011 +`define VLSEGD 32'b?????_?????_?????_0001000011_0001011 +`define VLSEGW 32'b?????_?????_?????_0001000010_0001011 +`define VLSEGWU 32'b?????_?????_?????_0001000110_0001011 +`define VLSEGH 32'b?????_?????_?????_0001000001_0001011 +`define VLSEGHU 32'b?????_?????_?????_0001000101_0001011 +`define VLSEGB 32'b?????_?????_?????_0001000000_0001011 +`define VLSEGBU 32'b?????_?????_?????_0001000100_0001011 +`define VFLSEGD 32'b?????_?????_?????_0001001011_0001011 +`define VFLSEGW 32'b?????_?????_?????_0001001010_0001011 +`define VLSEGSTD 32'b?????_?????_?????_?????_100_11_0001011 +`define VLSEGSTW 32'b?????_?????_?????_?????_100_10_0001011 +`define VLSEGSTWU 32'b?????_?????_?????_?????_101_10_0001011 +`define VLSEGSTH 32'b?????_?????_?????_?????_100_01_0001011 +`define VLSEGSTHU 32'b?????_?????_?????_?????_101_01_0001011 +`define VLSEGSTB 32'b?????_?????_?????_?????_100_00_0001011 +`define VLSEGSTBU 32'b?????_?????_?????_?????_101_00_0001011 +`define VFLSEGSTD 32'b?????_?????_?????_?????_110_11_0001011 +`define VFLSEGSTW 32'b?????_?????_?????_?????_110_10_0001011 +`define VSD 32'b?????_?????_00000_0000000011_0001111 +`define VSW 32'b?????_?????_00000_0000000010_0001111 +`define VSH 32'b?????_?????_00000_0000000001_0001111 +`define VSB 32'b?????_?????_00000_0000000000_0001111 +`define VFSD 32'b?????_?????_00000_0000001011_0001111 +`define VFSW 32'b?????_?????_00000_0000001010_0001111 +`define VSSTD 32'b?????_?????_?????_0000100011_0001111 +`define VSSTW 32'b?????_?????_?????_0000100010_0001111 +`define VSSTH 32'b?????_?????_?????_0000100001_0001111 +`define VSSTB 32'b?????_?????_?????_0000100000_0001111 +`define VFSSTD 32'b?????_?????_?????_0000101011_0001111 +`define VFSSTW 32'b?????_?????_?????_0000101010_0001111 +`define VSSEGD 32'b?????_?????_?????_0001000011_0001111 +`define VSSEGW 32'b?????_?????_?????_0001000010_0001111 +`define VSSEGH 32'b?????_?????_?????_0001000001_0001111 +`define VSSEGB 32'b?????_?????_?????_0001000000_0001111 +`define VFSSEGD 32'b?????_?????_?????_0001001011_0001111 +`define VFSSEGW 32'b?????_?????_?????_0001001010_0001111 +`define VSSEGSTD 32'b?????_?????_?????_?????_100_11_0001111 +`define VSSEGSTW 32'b?????_?????_?????_?????_100_10_0001111 +`define VSSEGSTH 32'b?????_?????_?????_?????_100_01_0001111 +`define VSSEGSTB 32'b?????_?????_?????_?????_100_00_0001111 +`define VFSSEGSTD 32'b?????_?????_?????_?????_110_11_0001111 +`define VFSSEGSTW 32'b?????_?????_?????_?????_110_10_0001111 +`define VMVV 32'b?????_?????_00000_0000000000_1110011 +`define VMSV 32'b?????_?????_00000_0000010000_1110011 +`define VMST 32'b?????_?????_?????_0000100000_1110011 +`define VMTS 32'b?????_?????_?????_0000110000_1110011 +`define VFMVV 32'b?????_?????_00000_0000000010_1110011 +`define VFMSV 32'b?????_?????_00000_0000010010_1110011 +`define VFMST 32'b?????_?????_?????_0000100010_1110011 +`define VFMTS 32'b?????_?????_?????_0000110010_1110011 +`define VVCFGIVL 32'b?????_?????_????????????_001_1110011 +`define VTCFGIVL 32'b?????_?????_????????????_011_1110011 +`define VSETVL 32'b?????_?????_000000000000_101_1110011 +`define VF 32'b00000_?????_????????????_111_1110011 `define C_LI 32'b00000000000000000000000000000000 `define C_ADDI 32'b00000000000000000000000000000000 `define C_ADDIW 32'b00000000000000000000000000000000 diff --git a/instr-table.tex b/instr-table.tex index 3ccc735..ee84667 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -2070,6 +2070,46 @@ \cline{2-11} +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{1110111} & MOVZ rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{1110111} & MOVN rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{110} & +\multicolumn{1}{c|}{1110111} & FMOVZ rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{111} & +\multicolumn{1}{c|}{1110111} & FMOVN rd,rs1,rs2 \\ +\cline{2-11} + + \end{tabular} \end{center} \end{small} @@ -122,6 +122,10 @@ fence.g.cv rd rs1 imm12 9..7=7 6..2=0x0B 1..0=3 # vector scalar instructions stop 31..27=0 26..22=0 21..17=0 16..7=2 6..2=0x1D 1..0=3 utidx rd 26..22=0 21..17=0 16..7=3 6..2=0x1D 1..0=3 +movz rd rs1 rs2 16..7=4 6..2=0x1D 1..0=3 +movn rd rs1 rs2 16..7=5 6..2=0x1D 1..0=3 +fmovz rd rs1 rs2 16..7=6 6..2=0x1D 1..0=3 +fmovn rd rs1 rs2 16..7=7 6..2=0x1D 1..0=3 ei rd 26..22=0 21..17=0 16..7=0 6..2=0x1E 1..0=3 di rd 26..22=0 21..17=0 16..7=1 6..2=0x1E 1..0=3 @@ -210,115 +214,129 @@ fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 -# vector mem instructions +# vector load mem instructions # 3=d # 2=seg 2=w -# 1=st 1=st 1=f 1=s 1=h -# 0=u 0=ld 0=x 0=u 0=b +# 1=st 1=seg 1=f 1=s 1=h +# 0=u 0=etc 0=x 0=u 0=b # ---------------------------------------------------------------------------- -# mem padding type ldst x/f u/s width opcode +# mem padding type seg x/f u/s width opcode # unit stride | | | | | | | | # xloads | | | | | | | | -ld.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lh.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lb.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# xstores -sd.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -sw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -sh.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -sb.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +vlw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +vlwu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +vlh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +vlhu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +vlb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlbu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 # floads -fld.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -flw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# fstores -fsd.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -fsw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +vfld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +vflw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# mem padding type ldst x/f u/s width opcode +# mem padding type seg x/f u/s width opcode # stride | | | | | | | | # xloads | | | | | | | | -ldst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lwst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lhst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lbst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# xstores -sdst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -swst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -shst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -sbst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +vlstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +vlstwu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +vlsth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +vlsthu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +vlstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlstbu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 # floads -fldst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -flwst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# fstores -fsdst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -fswst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +vflstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +vflstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# mem padding type ldst x/f u/s width opcode +# mem padding type seg x/f u/s width opcode # segment | | | | | | | | # xloads | | | | | | | | -ldseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lwseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lhseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lbseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# xstores -sdseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -swseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -shseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -sbseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +vlsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +vlsegwu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +vlsegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +vlseghu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +vlsegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlsegbu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 # floads -fldseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -flwseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# fstores -fsdseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -fswseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +vflsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +vflsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# ldst x/f u/s width opcode +# seg x/f u/s width opcode # stride segment | | | | | # xloads | | | | | -ldsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -lwsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 -lwusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=2 6..2=0x03 1..0=3 -lhsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 -lhusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=1 6..2=0x03 1..0=3 -lbsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 -lbusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=0 6..2=0x03 1..0=3 -# xstores -sdsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -swsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 -shsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3 -sbsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +vlsegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +vlsegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +vlsegstwu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +vlsegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +vlsegsthu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +vlsegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlsegstbu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3 # floads -fldsegst.v rd rs1 rs2 rs3 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -flwsegst.v rd rs1 rs2 rs3 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 +vflsegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +vflsegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 + +# vector store mem instructions +# mem padding type seg x/f u/s width opcode +# unit stride | | | | | | | | +# xstores | | | | | | | | +vsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +vsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +vsh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +vsb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +# fstores +vfsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +vfsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# mem padding type seg x/f u/s width opcode +# stride | | | | | | | | +# xstores | | | | | | | | +vsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +vsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +vssth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +vsstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +# fstores +vfsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +vfsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# mem padding type seg x/f u/s width opcode +# segment | | | | | | | | +# xstores | | | | | | | | +vssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +vssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +vssegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +vssegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +# fstores +vfssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +vfssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# seg x/f u/s width opcode +# stride segment | | | | | +# xstores | | | | | +vssegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +vssegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +vssegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +vssegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3 # fstores -fsdsegst.v rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -fswsegst.v rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -# vector arithmetic instructions -mov.vv rd rs1 21..17=0 16=1 15=0 14..12=0 11..7=0 6..2=0x02 1..0=3 -mov.sv rd rs1 21..17=0 16=1 15=0 14..12=0 11..7=1 6..2=0x02 1..0=3 -mov.su rd rs1 rs2 16=1 15=0 14..12=0 11..7=2 6..2=0x02 1..0=3 -mov.us rd rs1 rs2 16=1 15=0 14..12=0 11..7=3 6..2=0x02 1..0=3 -fmov.vv rd rs1 21..17=0 16=1 15=1 14..12=0 11..7=0 6..2=0x02 1..0=3 -fmov.sv rd rs1 21..17=0 16=1 15=1 14..12=0 11..7=1 6..2=0x02 1..0=3 -fmov.su rd rs1 rs2 16=1 15=1 14..12=0 11..7=2 6..2=0x02 1..0=3 -fmov.us rd rs1 rs2 16=1 15=1 14..12=0 11..7=3 6..2=0x02 1..0=3 - -# vector immediate instructions -vcfgivl rd rs1 imm12 9..7=0 6..2=0x1C 1..0=3 -setvl rd rs1 21..10=0 9..7=1 6..2=0x1C 1..0=3 -vf 31..27=0 rs1 imm12 9..7=2 6..2=0x1C 1..0=3 +vfssegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +vfssegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# other vector register instructions +vmvv rd rs1 21..17=0 16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3 +vmsv rd rs1 21..17=0 16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3 +vmst rd rs1 rs2 16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3 +vmts rd rs1 rs2 16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3 +vfmvv rd rs1 21..17=0 16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3 +vfmsv rd rs1 21..17=0 16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3 +vfmst rd rs1 rs2 16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3 +vfmts rd rs1 rs2 16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3 + +# other vector immediate instructions +vvcfgivl rd rs1 imm12 9..8=0 7=1 6..2=0x1C 1..0=3 +vtcfgivl rd rs1 imm12 9..8=1 7=1 6..2=0x1C 1..0=3 +vsetvl rd rs1 21..10=0 9..8=2 7=1 6..2=0x1C 1..0=3 +vf 31..27=0 rs1 imm12 9..8=3 7=1 6..2=0x1C 1..0=3 # compressed instructions c.li cimm6 crd 4..0=0 diff --git a/parse-opcodes b/parse-opcodes index c1d1845..4ebc638 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -35,7 +35,7 @@ arglut['cimm6'] = (15,10) arglut['cimm10'] = (14,5) arglut['cimm5'] = (9,5) -typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,10=b +typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,,8=r4rm,9=rrm,10=b typelut[0x03] = 3 typelut[0x07] = 3 typelut[0x13] = 3 @@ -66,8 +66,8 @@ for i in range(0,3): # vector opcodes typelut[0x0B] = 4 -typelut[0x0F] = 5 -typelut[0x73] = 3 +typelut[0x0F] = 4 +typelut[0x73] = 4 opcode_base = 0 opcode_size = 7 @@ -299,6 +299,27 @@ def print_r_type(name,match,arguments): str_inst(name,arguments) \ ) +def print_r4_type(name,match,arguments): + print """ +& +\\multicolumn{1}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{3}{c|}{%s} & +\\multicolumn{3}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-11} + """ % \ + ( \ + str_arg('rd','',match,arguments), \ + str_arg('rs1','',match,arguments), \ + str_arg('rs2','',match,arguments), \ + str_arg('rs3','',match,arguments), \ + binary(yank(match,7,5),5), \ + binary(yank(match,opcode_base,opcode_size),opcode_size), \ + str_inst(name,arguments) \ + ) + def print_r_rm_type(name,match,arguments): print """ & @@ -787,10 +808,14 @@ for line in sys.stdin: types[name] = 3 elif 'shamt' in arguments[name]: types[name] = 6 + elif types[name] == 4 and 'rs3' in arguments[name]: + types[name] = 5 elif types[name] == 5 and 'rm' in arguments[name]: types[name] = 8 elif types[name] == 4 and 'rm' in arguments[name]: types[name] = 9 + elif name == 'vsetvl': + types[name] = 3 namelist.append(name) |