temporary undoing of renaming

5 files changed, 3585 insertions, 0 deletions

diff --git a/Makefile b/Makefile
new file mode 100755
index 0000000..4cb4597
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,22 @@
+ISASIM_H := ../riscv-isa-run/riscv/opcodes.h
+PK_H := ../riscv-pk/pk/riscv-opc.h
+XCC_H := ../riscv-gcc/src/include/opcode/mips-riscv-opc.h
+
+install: $(ISASIM_H) $(PK_H) $(XCC_H) inst.v instr-table.tex
+
+$(ISASIM_H): opcodes parse-opcodes
+	./parse-opcodes -isasim < $< > $@
+
+$(PK_H): opcodes parse-opcodes
+	./parse-opcodes -disasm < $< > $@
+
+$(XCC_H): opcodes parse-opcodes
+	./parse-opcodes -disasm < $< > $@
+
+inst.v: opcodes parse-opcodes
+	./parse-opcodes -verilog < $< > $@
+
+instr-table.tex: opcodes parse-opcodes
+	./parse-opcodes -tex < $< > $@
+
+.PHONY : install
diff --git a/inst.v b/inst.v
new file mode 100644
index 0000000..fde166a
--- /dev/null
+++ b/inst.v
@@ -0,0 +1,273 @@
+/* Automatically generated by parse-opcodes */
+`define J          32'b?????????????????????????_1100111
+`define JAL        32'b?????????????????????????_1101111
+`define JALR_C     32'b?????_?????_????????????_000_1101011
+`define JALR_R     32'b?????_?????_????????????_001_1101011
+`define JALR_J     32'b?????_?????_????????????_010_1101011
+`define RDNPC      32'b?????_00000_000000000000_100_1101011
+`define BEQ        32'b?????_?????_?????_???????_000_1100011
+`define BNE        32'b?????_?????_?????_???????_001_1100011
+`define BLT        32'b?????_?????_?????_???????_100_1100011
+`define BGE        32'b?????_?????_?????_???????_101_1100011
+`define BLTU       32'b?????_?????_?????_???????_110_1100011
+`define BGEU       32'b?????_?????_?????_???????_111_1100011
+`define LUI        32'b?????_????????????????????_0110111
+`define ADDI       32'b?????_?????_????????????_000_0010011
+`define SLLI       32'b?????_?????_000000_??????_001_0010011
+`define SLTI       32'b?????_?????_????????????_010_0010011
+`define SLTIU      32'b?????_?????_????????????_011_0010011
+`define XORI       32'b?????_?????_????????????_100_0010011
+`define SRLI       32'b?????_?????_000000_??????_101_0010011
+`define SRAI       32'b?????_?????_000001_??????_101_0010011
+`define ORI        32'b?????_?????_????????????_110_0010011
+`define ANDI       32'b?????_?????_????????????_111_0010011
+`define ADD        32'b?????_?????_?????_0000000000_0110011
+`define SUB        32'b?????_?????_?????_1000000000_0110011
+`define SLL        32'b?????_?????_?????_0000000001_0110011
+`define SLT        32'b?????_?????_?????_0000000010_0110011
+`define SLTU       32'b?????_?????_?????_0000000011_0110011
+`define XOR        32'b?????_?????_?????_0000000100_0110011
+`define SRL        32'b?????_?????_?????_0000000101_0110011
+`define SRA        32'b?????_?????_?????_1000000101_0110011
+`define OR         32'b?????_?????_?????_0000000110_0110011
+`define AND        32'b?????_?????_?????_0000000111_0110011
+`define MUL        32'b?????_?????_?????_0000001000_0110011
+`define MULH       32'b?????_?????_?????_0000001001_0110011
+`define MULHSU     32'b?????_?????_?????_0000001010_0110011
+`define MULHU      32'b?????_?????_?????_0000001011_0110011
+`define DIV        32'b?????_?????_?????_0000001100_0110011
+`define DIVU       32'b?????_?????_?????_0000001101_0110011
+`define REM        32'b?????_?????_?????_0000001110_0110011
+`define REMU       32'b?????_?????_?????_0000001111_0110011
+`define ADDIW      32'b?????_?????_????????????_000_0011011
+`define SLLIW      32'b?????_?????_000000_0_?????_001_0011011
+`define SRLIW      32'b?????_?????_000000_0_?????_101_0011011
+`define SRAIW      32'b?????_?????_000001_0_?????_101_0011011
+`define ADDW       32'b?????_?????_?????_0000000000_0111011
+`define SUBW       32'b?????_?????_?????_1000000000_0111011
+`define SLLW       32'b?????_?????_?????_0000000001_0111011
+`define SRLW       32'b?????_?????_?????_0000000101_0111011
+`define SRAW       32'b?????_?????_?????_1000000101_0111011
+`define MULW       32'b?????_?????_?????_0000001000_0111011
+`define DIVW       32'b?????_?????_?????_0000001100_0111011
+`define DIVUW      32'b?????_?????_?????_0000001101_0111011
+`define REMW       32'b?????_?????_?????_0000001110_0111011
+`define REMUW      32'b?????_?????_?????_0000001111_0111011
+`define LB         32'b?????_?????_????????????_000_0000011
+`define LH         32'b?????_?????_????????????_001_0000011
+`define LW         32'b?????_?????_????????????_010_0000011
+`define LD         32'b?????_?????_????????????_011_0000011
+`define LBU        32'b?????_?????_????????????_100_0000011
+`define LHU        32'b?????_?????_????????????_101_0000011
+`define LWU        32'b?????_?????_????????????_110_0000011
+`define SB         32'b?????_?????_?????_???????_000_0100011
+`define SH         32'b?????_?????_?????_???????_001_0100011
+`define SW         32'b?????_?????_?????_???????_010_0100011
+`define SD         32'b?????_?????_?????_???????_011_0100011
+`define AMOADD_W   32'b?????_?????_?????_0000000010_0101011
+`define AMOSWAP_W  32'b?????_?????_?????_0000001010_0101011
+`define AMOAND_W   32'b?????_?????_?????_0000010010_0101011
+`define AMOOR_W    32'b?????_?????_?????_0000011010_0101011
+`define AMOMIN_W   32'b?????_?????_?????_0000100010_0101011
+`define AMOMAX_W   32'b?????_?????_?????_0000101010_0101011
+`define AMOMINU_W  32'b?????_?????_?????_0000110010_0101011
+`define AMOMAXU_W  32'b?????_?????_?????_0000111010_0101011
+`define AMOADD_D   32'b?????_?????_?????_0000000011_0101011
+`define AMOSWAP_D  32'b?????_?????_?????_0000001011_0101011
+`define AMOAND_D   32'b?????_?????_?????_0000010011_0101011
+`define AMOOR_D    32'b?????_?????_?????_0000011011_0101011
+`define AMOMIN_D   32'b?????_?????_?????_0000100011_0101011
+`define AMOMAX_D   32'b?????_?????_?????_0000101011_0101011
+`define AMOMINU_D  32'b?????_?????_?????_0000110011_0101011
+`define AMOMAXU_D  32'b?????_?????_?????_0000111011_0101011
+`define FENCE_I    32'b?????_?????_????????????_001_0101111
+`define FENCE      32'b?????_?????_????????????_010_0101111
+`define SYSCALL    32'b00000_00000_00000_0000000000_1110111
+`define BREAK      32'b00000_00000_00000_0000000001_1110111
+`define RDCYCLE    32'b?????_00000_00000_0000000100_1110111
+`define RDTIME     32'b?????_00000_00000_0000001100_1110111
+`define RDINSTRET  32'b?????_00000_00000_0000010100_1110111
+`define FENCE_L_V  32'b?????_?????_????????????_100_0101111
+`define FENCE_G_V  32'b?????_?????_????????????_101_0101111
+`define FENCE_L_CV 32'b?????_?????_????????????_110_0101111
+`define FENCE_G_CV 32'b?????_?????_????????????_111_0101111
+`define STOP       32'b00000_00000_00000_0000000010_1110111
+`define UTIDX      32'b?????_00000_00000_0000000011_1110111
+`define MOVZ       32'b?????_?????_?????_0000000101_1110111
+`define MOVN       32'b?????_?????_?????_0000001101_1110111
+`define FMOVZ      32'b?????_?????_?????_0000010101_1110111
+`define FMOVN      32'b?????_?????_?????_0000011101_1110111
+`define EI         32'b?????_00000_00000_0000000000_1111011
+`define DI         32'b?????_00000_00000_0000000001_1111011
+`define MFPCR      32'b?????_00000_?????_0000000010_1111011
+`define MTPCR      32'b00000_?????_?????_0000000011_1111011
+`define ERET       32'b00000_00000_00000_0000000100_1111011
+`define CFLUSH     32'b00000_00000_00000_0000000101_1111011
+`define FADD_S     32'b?????_?????_?????_00000_???_00_1010011
+`define FSUB_S     32'b?????_?????_?????_00001_???_00_1010011
+`define FMUL_S     32'b?????_?????_?????_00010_???_00_1010011
+`define FDIV_S     32'b?????_?????_?????_00011_???_00_1010011
+`define FSQRT_S    32'b?????_?????_00000_00100_???_00_1010011
+`define FSGNJ_S    32'b?????_?????_?????_00101_000_00_1010011
+`define FSGNJN_S   32'b?????_?????_?????_00110_000_00_1010011
+`define FSGNJX_S   32'b?????_?????_?????_00111_000_00_1010011
+`define FADD_D     32'b?????_?????_?????_00000_???_01_1010011
+`define FSUB_D     32'b?????_?????_?????_00001_???_01_1010011
+`define FMUL_D     32'b?????_?????_?????_00010_???_01_1010011
+`define FDIV_D     32'b?????_?????_?????_00011_???_01_1010011
+`define FSQRT_D    32'b?????_?????_00000_00100_???_01_1010011
+`define FSGNJ_D    32'b?????_?????_?????_00101_000_01_1010011
+`define FSGNJN_D   32'b?????_?????_?????_00110_000_01_1010011
+`define FSGNJX_D   32'b?????_?????_?????_00111_000_01_1010011
+`define FCVT_L_S   32'b?????_?????_00000_01000_???_00_1010011
+`define FCVT_LU_S  32'b?????_?????_00000_01001_???_00_1010011
+`define FCVT_W_S   32'b?????_?????_00000_01010_???_00_1010011
+`define FCVT_WU_S  32'b?????_?????_00000_01011_???_00_1010011
+`define FCVT_L_D   32'b?????_?????_00000_01000_???_01_1010011
+`define FCVT_LU_D  32'b?????_?????_00000_01001_???_01_1010011
+`define FCVT_W_D   32'b?????_?????_00000_01010_???_01_1010011
+`define FCVT_WU_D  32'b?????_?????_00000_01011_???_01_1010011
+`define FCVT_S_L   32'b?????_?????_00000_01100_???_00_1010011
+`define FCVT_S_LU  32'b?????_?????_00000_01101_???_00_1010011
+`define FCVT_S_W   32'b?????_?????_00000_01110_???_00_1010011
+`define FCVT_S_WU  32'b?????_?????_00000_01111_???_00_1010011
+`define FCVT_D_L   32'b?????_?????_00000_01100_???_01_1010011
+`define FCVT_D_LU  32'b?????_?????_00000_01101_???_01_1010011
+`define FCVT_D_W   32'b?????_?????_00000_01110_???_01_1010011
+`define FCVT_D_WU  32'b?????_?????_00000_01111_???_01_1010011
+`define FCVT_S_D   32'b?????_?????_00000_10001_???_00_1010011
+`define FCVT_D_S   32'b?????_?????_00000_10000_???_01_1010011
+`define FEQ_S      32'b?????_?????_?????_10101_000_00_1010011
+`define FLT_S      32'b?????_?????_?????_10110_000_00_1010011
+`define FLE_S      32'b?????_?????_?????_10111_000_00_1010011
+`define FEQ_D      32'b?????_?????_?????_10101_000_01_1010011
+`define FLT_D      32'b?????_?????_?????_10110_000_01_1010011
+`define FLE_D      32'b?????_?????_?????_10111_000_01_1010011
+`define FMIN_S     32'b?????_?????_?????_11000_000_00_1010011
+`define FMAX_S     32'b?????_?????_?????_11001_000_00_1010011
+`define FMIN_D     32'b?????_?????_?????_11000_000_01_1010011
+`define FMAX_D     32'b?????_?????_?????_11001_000_01_1010011
+`define MFTX_S     32'b?????_00000_?????_11100_000_00_1010011
+`define MFTX_D     32'b?????_00000_?????_11100_000_01_1010011
+`define MFFSR      32'b?????_00000_00000_11101_000_00_1010011
+`define MXTF_S     32'b?????_?????_00000_11110_000_00_1010011
+`define MXTF_D     32'b?????_?????_00000_11110_000_01_1010011
+`define MTFSR      32'b?????_?????_00000_11111_000_00_1010011
+`define FLW        32'b?????_?????_????????????_010_0000111
+`define FLD        32'b?????_?????_????????????_011_0000111
+`define FSW        32'b?????_?????_?????_???????_010_0100111
+`define FSD        32'b?????_?????_?????_???????_011_0100111
+`define FMADD_S    32'b?????_?????_?????_?????_???_00_1000011
+`define FMSUB_S    32'b?????_?????_?????_?????_???_00_1000111
+`define FNMSUB_S   32'b?????_?????_?????_?????_???_00_1001011
+`define FNMADD_S   32'b?????_?????_?????_?????_???_00_1001111
+`define FMADD_D    32'b?????_?????_?????_?????_???_01_1000011
+`define FMSUB_D    32'b?????_?????_?????_?????_???_01_1000111
+`define FNMSUB_D   32'b?????_?????_?????_?????_???_01_1001011
+`define FNMADD_D   32'b?????_?????_?????_?????_???_01_1001111
+`define VLD        32'b?????_?????_00000_0000000011_0001011
+`define VLW        32'b?????_?????_00000_0000000010_0001011
+`define VLWU       32'b?????_?????_00000_0000000110_0001011
+`define VLH        32'b?????_?????_00000_0000000001_0001011
+`define VLHU       32'b?????_?????_00000_0000000101_0001011
+`define VLB        32'b?????_?????_00000_0000000000_0001011
+`define VLBU       32'b?????_?????_00000_0000000100_0001011
+`define VFLD       32'b?????_?????_00000_0000001011_0001011
+`define VFLW       32'b?????_?????_00000_0000001010_0001011
+`define VLSTD      32'b?????_?????_?????_0000100011_0001011
+`define VLSTW      32'b?????_?????_?????_0000100010_0001011
+`define VLSTWU     32'b?????_?????_?????_0000100110_0001011
+`define VLSTH      32'b?????_?????_?????_0000100001_0001011
+`define VLSTHU     32'b?????_?????_?????_0000100101_0001011
+`define VLSTB      32'b?????_?????_?????_0000100000_0001011
+`define VLSTBU     32'b?????_?????_?????_0000100100_0001011
+`define VFLSTD     32'b?????_?????_?????_0000101011_0001011
+`define VFLSTW     32'b?????_?????_?????_0000101010_0001011
+`define VLSEGD     32'b?????_?????_?????_0001000011_0001011
+`define VLSEGW     32'b?????_?????_?????_0001000010_0001011
+`define VLSEGWU    32'b?????_?????_?????_0001000110_0001011
+`define VLSEGH     32'b?????_?????_?????_0001000001_0001011
+`define VLSEGHU    32'b?????_?????_?????_0001000101_0001011
+`define VLSEGB     32'b?????_?????_?????_0001000000_0001011
+`define VLSEGBU    32'b?????_?????_?????_0001000100_0001011
+`define VFLSEGD    32'b?????_?????_?????_0001001011_0001011
+`define VFLSEGW    32'b?????_?????_?????_0001001010_0001011
+`define VLSEGSTD   32'b?????_?????_?????_?????_100_11_0001011
+`define VLSEGSTW   32'b?????_?????_?????_?????_100_10_0001011
+`define VLSEGSTWU  32'b?????_?????_?????_?????_101_10_0001011
+`define VLSEGSTH   32'b?????_?????_?????_?????_100_01_0001011
+`define VLSEGSTHU  32'b?????_?????_?????_?????_101_01_0001011
+`define VLSEGSTB   32'b?????_?????_?????_?????_100_00_0001011
+`define VLSEGSTBU  32'b?????_?????_?????_?????_101_00_0001011
+`define VFLSEGSTD  32'b?????_?????_?????_?????_110_11_0001011
+`define VFLSEGSTW  32'b?????_?????_?????_?????_110_10_0001011
+`define VSD        32'b?????_?????_00000_0000000011_0001111
+`define VSW        32'b?????_?????_00000_0000000010_0001111
+`define VSH        32'b?????_?????_00000_0000000001_0001111
+`define VSB        32'b?????_?????_00000_0000000000_0001111
+`define VFSD       32'b?????_?????_00000_0000001011_0001111
+`define VFSW       32'b?????_?????_00000_0000001010_0001111
+`define VSSTD      32'b?????_?????_?????_0000100011_0001111
+`define VSSTW      32'b?????_?????_?????_0000100010_0001111
+`define VSSTH      32'b?????_?????_?????_0000100001_0001111
+`define VSSTB      32'b?????_?????_?????_0000100000_0001111
+`define VFSSTD     32'b?????_?????_?????_0000101011_0001111
+`define VFSSTW     32'b?????_?????_?????_0000101010_0001111
+`define VSSEGD     32'b?????_?????_?????_0001000011_0001111
+`define VSSEGW     32'b?????_?????_?????_0001000010_0001111
+`define VSSEGH     32'b?????_?????_?????_0001000001_0001111
+`define VSSEGB     32'b?????_?????_?????_0001000000_0001111
+`define VFSSEGD    32'b?????_?????_?????_0001001011_0001111
+`define VFSSEGW    32'b?????_?????_?????_0001001010_0001111
+`define VSSEGSTD   32'b?????_?????_?????_?????_100_11_0001111
+`define VSSEGSTW   32'b?????_?????_?????_?????_100_10_0001111
+`define VSSEGSTH   32'b?????_?????_?????_?????_100_01_0001111
+`define VSSEGSTB   32'b?????_?????_?????_?????_100_00_0001111
+`define VFSSEGSTD  32'b?????_?????_?????_?????_110_11_0001111
+`define VFSSEGSTW  32'b?????_?????_?????_?????_110_10_0001111
+`define VMVV       32'b?????_?????_00000_0000000000_1110011
+`define VMSV       32'b?????_?????_00000_0000010000_1110011
+`define VMST       32'b?????_?????_?????_0000100000_1110011
+`define VMTS       32'b?????_?????_?????_0000110000_1110011
+`define VFMVV      32'b?????_?????_00000_0000000010_1110011
+`define VFMSV      32'b?????_?????_00000_0000010010_1110011
+`define VFMST      32'b?????_?????_?????_0000100010_1110011
+`define VFMTS      32'b?????_?????_?????_0000110010_1110011
+`define VVCFGIVL   32'b?????_?????_????????????_001_1110011
+`define VTCFGIVL   32'b?????_?????_????????????_011_1110011
+`define VSETVL     32'b?????_?????_000000000000_101_1110011
+`define VF         32'b00000_?????_????????????_111_1110011
+`define C_LI       32'b00000000000000000000000000000000
+`define C_ADDI     32'b00000000000000000000000000000000
+`define C_ADDIW    32'b00000000000000000000000000000000
+`define C_LDSP     32'b00000000000000000000000000000000
+`define C_LWSP     32'b00000000000000000000000000000000
+`define C_SDSP     32'b00000000000000000000000000000000
+`define C_SWSP     32'b00000000000000000000000000000000
+`define C_LW0      32'b00000000000000000000000000000000
+`define C_LD0      32'b00000000000000000000000000000000
+`define C_ADD      32'b00000000000000000000000000000000
+`define C_SUB      32'b00000000000000000000000000000000
+`define C_MOVE     32'b00000000000000000000000000000000
+`define C_J        32'b00000000000000000000000000000000
+`define C_LD       32'b00000000000000000000000000000000
+`define C_LW       32'b00000000000000000000000000000000
+`define C_SD       32'b00000000000000000000000000000000
+`define C_SW       32'b00000000000000000000000000000000
+`define C_BEQ      32'b00000000000000000000000000000000
+`define C_BNE      32'b00000000000000000000000000000000
+`define C_FLW      32'b00000000000000000000000000000000
+`define C_FLD      32'b00000000000000000000000000000000
+`define C_FSW      32'b00000000000000000000000000000000
+`define C_FSD      32'b00000000000000000000000000000000
+`define C_SLLI     32'b00000000000000000000000000000000
+`define C_SLLI32   32'b00000000000000000000000000000000
+`define C_SRLI     32'b00000000000000000000000000000000
+`define C_SRLI32   32'b00000000000000000000000000000000
+`define C_SRAI     32'b00000000000000000000000000000000
+`define C_SRAI32   32'b00000000000000000000000000000000
+`define C_SLLIW    32'b00000000000000000000000000000000
+`define C_ADD3     32'b00000000000000000000000000000000
+`define C_SUB3     32'b00000000000000000000000000000000
+`define C_OR3      32'b00000000000000000000000000000000
+`define C_AND3     32'b00000000000000000000000000000000
diff --git a/instr-table.tex b/instr-table.tex
new file mode 100644
index 0000000..241c769
--- /dev/null
+++ b/instr-table.tex
@@ -0,0 +1,2119 @@
+
+\newpage
+
+\begin{table}[p]
+\begin{small}
+\begin{center}
+\begin{tabular}{rccccccccccl}
+                &
+\hspace*{0.6in} &
+\hspace*{0.3in} &
+\hspace*{0.1in} &
+\hspace*{0.1in} &
+\hspace*{0.2in} &
+\hspace*{0.2in} &
+\hspace*{0.1in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} \\
+                      &
+\instbitrange{31}{27} &
+\instbitrange{26}{22} &
+\instbitrange{21}{17} &
+\instbit{16} &
+\instbit{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{10} &
+\instbit{9} &
+\instbitrange{8}{7} &
+\instbitrange{6}{0} \\
+\cline{2-11}
+&
+\multicolumn{9}{|c|}{jump target} &
+\multicolumn{1}{c|}{opcode} & J-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{8}{c|}{LUI-immediate} &
+\multicolumn{1}{c|}{opcode} & LUI-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{imm[11:7]} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & I-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{imm[11:7]} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & B-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{6}{c|}{funct10} &
+\multicolumn{1}{c|}{opcode} & R-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{3}{c|}{funct5} &
+\multicolumn{1}{c|}{opcode} & R4-type \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Unimplemented Instruction} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{|c|}{00000000000000000000000000000000} & UNIMP \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Control Transfer Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{9}{|c|}{imm25} &
+\multicolumn{1}{c|}{1100111} & J imm25 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{9}{|c|}{imm25} &
+\multicolumn{1}{c|}{1101111} & JAL imm25 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{1100011} & BEQ rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{1100011} & BNE rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{1100011} & BLT rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{1100011} & BGE rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{110} &
+\multicolumn{1}{c|}{1100011} & BLTU rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{111} &
+\multicolumn{1}{c|}{1100011} & BGEU rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{1101011} & JALR.C rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{1101011} & JALR.R rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{1101011} & JALR.J rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{5}{c|}{000000000000} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{1101011} & RDNPC rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Memory Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0000011} & LB rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{0000011} & LH rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0000011} & LW rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0000011} & LD rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{0000011} & LBU rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0000011} & LHU rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{110} &
+\multicolumn{1}{c|}{0000011} & LWU rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0100011} & SB rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{0100011} & SH rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0100011} & SW rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0100011} & SD rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Atomic Memory Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101011} & AMOADD.W rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101011} & AMOSWAP.W rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000010} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101011} & AMOAND.W rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000011} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101011} & AMOOR.W rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000100} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101011} & AMOMIN.W rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000101} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101011} & AMOMAX.W rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000110} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101011} & AMOMINU.W rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000111} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101011} & AMOMAXU.W rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0101011} & AMOADD.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0101011} & AMOSWAP.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000010} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0101011} & AMOAND.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000011} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0101011} & AMOOR.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000100} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0101011} & AMOMIN.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000101} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0101011} & AMOMAX.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000110} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0101011} & AMOMINU.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000111} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0101011} & AMOMAXU.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+\end{tabular}
+\end{center}
+\end{small}
+
+\label{instr-table}
+\end{table}
+  
+
+\newpage
+
+\begin{table}[p]
+\begin{small}
+\begin{center}
+\begin{tabular}{rccccccccccl}
+                &
+\hspace*{0.6in} &
+\hspace*{0.3in} &
+\hspace*{0.1in} &
+\hspace*{0.1in} &
+\hspace*{0.2in} &
+\hspace*{0.2in} &
+\hspace*{0.1in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} \\
+                      &
+\instbitrange{31}{27} &
+\instbitrange{26}{22} &
+\instbitrange{21}{17} &
+\instbit{16} &
+\instbit{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{10} &
+\instbit{9} &
+\instbitrange{8}{7} &
+\instbitrange{6}{0} \\
+\cline{2-11}
+&
+\multicolumn{9}{|c|}{jump target} &
+\multicolumn{1}{c|}{opcode} & J-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{8}{c|}{LUI-immediate} &
+\multicolumn{1}{c|}{opcode} & LUI-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{imm[11:7]} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & I-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{imm[11:7]} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & B-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{6}{c|}{funct10} &
+\multicolumn{1}{c|}{opcode} & R-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{3}{c|}{funct5} &
+\multicolumn{1}{c|}{opcode} & R4-type \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Integer Compute Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0010011} & ADDI rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{2}{c|}{000000} &
+\multicolumn{3}{c|}{shamt} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{0010011} & SLLI rd,rs1,shamt \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0010011} & SLTI rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0010011} & SLTIU rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{0010011} & XORI rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{2}{c|}{000000} &
+\multicolumn{3}{c|}{shamt} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0010011} & SRLI rd,rs1,shamt \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{2}{c|}{000001} &
+\multicolumn{3}{c|}{shamt} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0010011} & SRAI rd,rs1,shamt \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{110} &
+\multicolumn{1}{c|}{0010011} & ORI rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{111} &
+\multicolumn{1}{c|}{0010011} & ANDI rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0110011} & ADD rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{1000000} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0110011} & SUB rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{0110011} & SLL rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0110011} & SLT rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0110011} & SLTU rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{0110011} & XOR rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0110011} & SRL rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{1000000} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0110011} & SRA rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{110} &
+\multicolumn{1}{c|}{0110011} & OR rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{111} &
+\multicolumn{1}{c|}{0110011} & AND rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0110011} & MUL rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{0110011} & MULH rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0110011} & MULHSU rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0110011} & MULHU rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{0110011} & DIV rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0110011} & DIVU rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{110} &
+\multicolumn{1}{c|}{0110011} & REM rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{111} &
+\multicolumn{1}{c|}{0110011} & REMU rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{8}{c|}{imm20} &
+\multicolumn{1}{c|}{0110111} & LUI rd,imm20 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf 32-bit Integer Compute Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0011011} & ADDIW rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{3}{c|}{0000000} &
+\multicolumn{2}{c|}{shamtw} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{0011011} & SLLIW rd,rs1,shamtw \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{3}{c|}{0000000} &
+\multicolumn{2}{c|}{shamtw} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0011011} & SRLIW rd,rs1,shamtw \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{3}{c|}{0000010} &
+\multicolumn{2}{c|}{shamtw} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0011011} & SRAIW rd,rs1,shamtw \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0111011} & ADDW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{1000000} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0111011} & SUBW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{0111011} & SLLW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0111011} & SRLW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{1000000} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0111011} & SRAW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{0111011} & MULW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{0111011} & DIVW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0111011} & DIVUW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{110} &
+\multicolumn{1}{c|}{0111011} & REMW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{111} &
+\multicolumn{1}{c|}{0111011} & REMUW rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+\end{tabular}
+\end{center}
+\end{small}
+
+\label{instr-table}
+\end{table}
+  
+
+\newpage
+
+\begin{table}[p]
+\begin{small}
+\begin{center}
+\begin{tabular}{rccccccccccl}
+                &
+\hspace*{0.6in} &
+\hspace*{0.3in} &
+\hspace*{0.1in} &
+\hspace*{0.1in} &
+\hspace*{0.2in} &
+\hspace*{0.2in} &
+\hspace*{0.1in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} \\
+                      &
+\instbitrange{31}{27} &
+\instbitrange{26}{22} &
+\instbitrange{21}{17} &
+\instbit{16} &
+\instbit{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{10} &
+\instbit{9} &
+\instbitrange{8}{7} &
+\instbitrange{6}{0} \\
+\cline{2-11}
+&
+\multicolumn{9}{|c|}{jump target} &
+\multicolumn{1}{c|}{opcode} & J-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{8}{c|}{LUI-immediate} &
+\multicolumn{1}{c|}{opcode} & LUI-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{imm[11:7]} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & I-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{imm[11:7]} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & B-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{6}{c|}{funct10} &
+\multicolumn{1}{c|}{opcode} & R-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{3}{c|}{funct5} &
+\multicolumn{1}{c|}{opcode} & R4-type \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Floating-Point Memory Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0000111} & FLW rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0000111} & FLD rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0100111} & FSW rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{imm12hi} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm12lo} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{0100111} & FSD rs1,rs2,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Floating-Point Compute Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00000} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FADD.S rd,rs1,rs2[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00001} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FSUB.S rd,rs1,rs2[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00010} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FMUL.S rd,rs1,rs2[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00011} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FDIV.S rd,rs1,rs2[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{00100} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FSQRT.S rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{11000} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FMIN.S rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{11001} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FMAX.S rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00000} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FADD.D rd,rs1,rs2[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00001} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FSUB.D rd,rs1,rs2[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00010} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FMUL.D rd,rs1,rs2[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00011} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FDIV.D rd,rs1,rs2[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{00100} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FSQRT.D rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{11000} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FMIN.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{11001} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FMAX.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1000011} & FMADD.S rd,rs1,rs2,rs3[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1000111} & FMSUB.S rd,rs1,rs2,rs3[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1001011} & FNMSUB.S rd,rs1,rs2,rs3[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1001111} & FNMADD.S rd,rs1,rs2,rs3[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1000011} & FMADD.D rd,rs1,rs2,rs3[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1000111} & FMSUB.D rd,rs1,rs2,rs3[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1001011} & FNMSUB.D rd,rs1,rs2,rs3[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1001111} & FNMADD.D rd,rs1,rs2,rs3[,rm] \\
+\cline{2-11}
+  
+
+\end{tabular}
+\end{center}
+\end{small}
+
+\label{instr-table}
+\end{table}
+  
+
+\newpage
+
+\begin{table}[p]
+\begin{small}
+\begin{center}
+\begin{tabular}{rccccccccccl}
+                &
+\hspace*{0.6in} &
+\hspace*{0.3in} &
+\hspace*{0.1in} &
+\hspace*{0.1in} &
+\hspace*{0.2in} &
+\hspace*{0.2in} &
+\hspace*{0.1in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} \\
+                      &
+\instbitrange{31}{27} &
+\instbitrange{26}{22} &
+\instbitrange{21}{17} &
+\instbit{16} &
+\instbit{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{10} &
+\instbit{9} &
+\instbitrange{8}{7} &
+\instbitrange{6}{0} \\
+\cline{2-11}
+&
+\multicolumn{9}{|c|}{jump target} &
+\multicolumn{1}{c|}{opcode} & J-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{8}{c|}{LUI-immediate} &
+\multicolumn{1}{c|}{opcode} & LUI-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{imm[11:7]} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & I-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{imm[11:7]} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & B-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{6}{c|}{funct10} &
+\multicolumn{1}{c|}{opcode} & R-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{3}{c|}{funct5} &
+\multicolumn{1}{c|}{opcode} & R4-type \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Floating-Point Move \& Conversion Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00101} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FSGNJ.S rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FSGNJN.S rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00111} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FSGNJX.S rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00101} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FSGNJ.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FSGNJN.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{00111} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FSGNJX.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{10001} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.S.D rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{10000} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.D.S rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Integer to Floating-Point Move \& Conversion Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01100} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.S.L rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01101} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.S.LU rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01110} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.S.W rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01111} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.S.WU rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01100} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.D.L rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01101} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.D.LU rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01110} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.D.W rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01111} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.D.WU rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{11110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & MXTF.S rd,rs1 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{11110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & MXTF.D rd,rs1 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{11111} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & MTFSR rd,rs1 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Floating-Point to Integer Move \& Conversion Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01000} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.L.S rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01001} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.LU.S rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01010} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.W.S rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01011} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FCVT.WU.S rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01000} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.L.D rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01001} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.LU.D rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01010} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.W.D rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{01011} &
+\multicolumn{2}{c|}{rm} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FCVT.WU.D rd,rs1[,rm] \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{11100} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & MFTX.S rd,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{11100} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & MFTX.D rd,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{11101} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & MFFSR rd \\
+\cline{2-11}
+  
+
+\end{tabular}
+\end{center}
+\end{small}
+
+\label{instr-table}
+\end{table}
+  
+
+\newpage
+
+\begin{table}[p]
+\begin{small}
+\begin{center}
+\begin{tabular}{rccccccccccl}
+                &
+\hspace*{0.6in} &
+\hspace*{0.3in} &
+\hspace*{0.1in} &
+\hspace*{0.1in} &
+\hspace*{0.2in} &
+\hspace*{0.2in} &
+\hspace*{0.1in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} &
+\hspace*{0.3in} \\
+                      &
+\instbitrange{31}{27} &
+\instbitrange{26}{22} &
+\instbitrange{21}{17} &
+\instbit{16} &
+\instbit{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{10} &
+\instbit{9} &
+\instbitrange{8}{7} &
+\instbitrange{6}{0} \\
+\cline{2-11}
+&
+\multicolumn{9}{|c|}{jump target} &
+\multicolumn{1}{c|}{opcode} & J-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{8}{c|}{LUI-immediate} &
+\multicolumn{1}{c|}{opcode} & LUI-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{imm[11:7]} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & I-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{imm[11:7]} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{imm[6:0]} &
+\multicolumn{2}{c|}{funct3} &
+\multicolumn{1}{c|}{opcode} & B-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{6}{c|}{funct10} &
+\multicolumn{1}{c|}{opcode} & R-type \\
+\cline{2-11}
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{rs3} &
+\multicolumn{3}{c|}{funct5} &
+\multicolumn{1}{c|}{opcode} & R4-type \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Floating-Point Compare Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{10101} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FEQ.S rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{10110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FLT.S rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{10111} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FLE.S rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{10101} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FEQ.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{10110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FLT.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{10111} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
+\multicolumn{1}{c|}{1010011} & FLE.D rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf Miscellaneous Memory Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{0101111} & FENCE.I rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{0101111} & FENCE rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{0101111} & FENCE.L.V rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{0101111} & FENCE.G.V rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{110} &
+\multicolumn{1}{c|}{0101111} & FENCE.L.CV rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{5}{c|}{imm12} &
+\multicolumn{2}{c|}{111} &
+\multicolumn{1}{c|}{0101111} & FENCE.G.CV rd,rs1,imm12 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{10}{c}{} & \\
+&
+\multicolumn{10}{c}{\bf System Instructions} & \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{1110111} & SYSCALL  \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{001} &
+\multicolumn{1}{c|}{1110111} & BREAK  \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{1110111} & RDCYCLE rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{1110111} & RDTIME rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000010} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{1110111} & RDINSTRET rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{010} &
+\multicolumn{1}{c|}{1110111} & STOP  \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{011} &
+\multicolumn{1}{c|}{1110111} & UTIDX rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{1110111} & MOVZ rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{1110111} & MOVN rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000010} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{1110111} & FMOVZ rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{4}{c|}{0000011} &
+\multicolumn{2}{c|}{101} &
+\multicolumn{1}{c|}{1110111} & FMOVN rd,rs1,rs2 \\
+\cline{2-11}
+  
+
+\end{tabular}
+\end{center}
+\end{small}
+\caption{Instruction listing for RISC-V}
+\label{instr-table}
+\end{table}
+  
diff --git a/opcodes b/opcodes
new file mode 100644
index 0000000..b559429
--- /dev/null
+++ b/opcodes
@@ -0,0 +1,380 @@
+# format of a line in this file:
+# <instruction name> <opcode> <args>
+#
+# <opcode> is given by specifying one or more range/value pairs:
+# highbit..lowbit=value (e.g. 6..2=0x45 9..7=0x0)
+#
+# <args> is one of xa,xb,xc,fa,fb,fc,fd,imm,imm20,imm27,shamt,shamtw
+
+j       imm25 6..2=0x19 1..0=3
+jal     imm25 6..2=0x1B 1..0=3
+
+jalr.c  rd rs1      imm12    9..7=0 6..2=0x1A 1..0=3
+jalr.r  rd rs1      imm12    9..7=1 6..2=0x1A 1..0=3
+jalr.j  rd rs1      imm12    9..7=2 6..2=0x1A 1..0=3
+rdnpc   rd 26..22=0 21..10=0 9..7=4 6..2=0x1A 1..0=3
+
+beq     imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x18 1..0=3
+bne     imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x18 1..0=3
+blt     imm12hi rs1 rs2 imm12lo 9..7=4 6..2=0x18 1..0=3
+bge     imm12hi rs1 rs2 imm12lo 9..7=5 6..2=0x18 1..0=3
+bltu    imm12hi rs1 rs2 imm12lo 9..7=6 6..2=0x18 1..0=3
+bgeu    imm12hi rs1 rs2 imm12lo 9..7=7 6..2=0x18 1..0=3
+
+lui     rd imm20 6..2=0x0D 1..0=3
+
+addi    rd rs1 imm12               9..7=0 6..2=0x04 1..0=3
+slli    rd rs1 21..17=0 16=0 shamt 9..7=1 6..2=0x04 1..0=3
+slti    rd rs1 imm12               9..7=2 6..2=0x04 1..0=3
+sltiu   rd rs1 imm12               9..7=3 6..2=0x04 1..0=3
+xori    rd rs1 imm12               9..7=4 6..2=0x04 1..0=3
+srli    rd rs1 21..17=0 16=0 shamt 9..7=5 6..2=0x04 1..0=3
+srai    rd rs1 21..17=0 16=1 shamt 9..7=5 6..2=0x04 1..0=3
+ori     rd rs1 imm12               9..7=6 6..2=0x04 1..0=3
+andi    rd rs1 imm12               9..7=7 6..2=0x04 1..0=3
+
+add     rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0C 1..0=3
+sub     rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0C 1..0=3
+sll     rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0C 1..0=3
+slt     rd rs1 rs2 16=0 15..10=0 9..7=2 6..2=0x0C 1..0=3
+sltu    rd rs1 rs2 16=0 15..10=0 9..7=3 6..2=0x0C 1..0=3
+xor     rd rs1 rs2 16=0 15..10=0 9..7=4 6..2=0x0C 1..0=3
+srl     rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0C 1..0=3
+sra     rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0C 1..0=3
+or      rd rs1 rs2 16=0 15..10=0 9..7=6 6..2=0x0C 1..0=3
+and     rd rs1 rs2 16=0 15..10=0 9..7=7 6..2=0x0C 1..0=3
+
+mul     rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0C 1..0=3
+mulh    rd rs1 rs2 16=0 15..10=1 9..7=1 6..2=0x0C 1..0=3
+mulhsu  rd rs1 rs2 16=0 15..10=1 9..7=2 6..2=0x0C 1..0=3
+mulhu   rd rs1 rs2 16=0 15..10=1 9..7=3 6..2=0x0C 1..0=3
+div     rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0C 1..0=3
+divu    rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0C 1..0=3
+rem     rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0C 1..0=3
+remu    rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0C 1..0=3
+
+addiw   rd rs1 imm12                     9..7=0 6..2=0x06 1..0=3
+slliw   rd rs1 21..17=0 16=0 15=0 shamtw 9..7=1 6..2=0x06 1..0=3
+srliw   rd rs1 21..17=0 16=0 15=0 shamtw 9..7=5 6..2=0x06 1..0=3
+sraiw   rd rs1 21..17=0 16=1 15=0 shamtw 9..7=5 6..2=0x06 1..0=3
+
+addw    rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0E 1..0=3
+subw    rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0E 1..0=3
+sllw    rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0E 1..0=3
+srlw    rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0E 1..0=3
+sraw    rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0E 1..0=3
+
+mulw    rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0E 1..0=3
+divw    rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0E 1..0=3
+divuw   rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0E 1..0=3
+remw    rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0E 1..0=3
+remuw   rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0E 1..0=3
+
+lb      rd rs1       imm12 9..7=0 6..2=0x00 1..0=3
+lh      rd rs1       imm12 9..7=1 6..2=0x00 1..0=3
+lw      rd rs1       imm12 9..7=2 6..2=0x00 1..0=3
+ld      rd rs1       imm12 9..7=3 6..2=0x00 1..0=3
+lbu     rd rs1       imm12 9..7=4 6..2=0x00 1..0=3
+lhu     rd rs1       imm12 9..7=5 6..2=0x00 1..0=3
+lwu     rd rs1       imm12 9..7=6 6..2=0x00 1..0=3
+
+# NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c
+# and elfxx-mips.c to detect them.  this is a hack to handle the split immed.
+# just open up those files and search for MATCH_SW; should be obvious.
+sb     imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x08 1..0=3
+sh     imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x08 1..0=3
+sw     imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x08 1..0=3
+sd     imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x08 1..0=3
+
+amoadd.w    rd rs1 rs2 16..10=0 9..7=2 6..2=0x0A 1..0=3
+amoswap.w   rd rs1 rs2 16..10=1 9..7=2 6..2=0x0A 1..0=3
+amoand.w    rd rs1 rs2 16..10=2 9..7=2 6..2=0x0A 1..0=3
+amoor.w     rd rs1 rs2 16..10=3 9..7=2 6..2=0x0A 1..0=3
+amomin.w    rd rs1 rs2 16..10=4 9..7=2 6..2=0x0A 1..0=3
+amomax.w    rd rs1 rs2 16..10=5 9..7=2 6..2=0x0A 1..0=3
+amominu.w   rd rs1 rs2 16..10=6 9..7=2 6..2=0x0A 1..0=3
+amomaxu.w   rd rs1 rs2 16..10=7 9..7=2 6..2=0x0A 1..0=3
+                                        
+amoadd.d     rd rs1 rs2 16..10=0 9..7=3 6..2=0x0A 1..0=3
+amoswap.d    rd rs1 rs2 16..10=1 9..7=3 6..2=0x0A 1..0=3
+amoand.d     rd rs1 rs2 16..10=2 9..7=3 6..2=0x0A 1..0=3
+amoor.d      rd rs1 rs2 16..10=3 9..7=3 6..2=0x0A 1..0=3
+amomin.d     rd rs1 rs2 16..10=4 9..7=3 6..2=0x0A 1..0=3
+amomax.d     rd rs1 rs2 16..10=5 9..7=3 6..2=0x0A 1..0=3
+amominu.d    rd rs1 rs2 16..10=6 9..7=3 6..2=0x0A 1..0=3
+amomaxu.d    rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3
+
+fence.i     rd rs1 imm12 9..7=1 6..2=0x0B 1..0=3
+fence       rd rs1 imm12 9..7=2 6..2=0x0B 1..0=3
+
+syscall   31..27=0 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x1D 1..0=3
+break     31..27=0 26..22=0 21..17=0 16..10=0 9..7=1 6..2=0x1D 1..0=3
+rdcycle   rd       26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1D 1..0=3
+rdtime    rd       26..22=0 21..17=0 16..10=1 9..7=4 6..2=0x1D 1..0=3
+rdinstret rd       26..22=0 21..17=0 16..10=2 9..7=4 6..2=0x1D 1..0=3
+
+# vector fence instructions
+fence.l.v   rd rs1 imm12 9..7=4 6..2=0x0B 1..0=3
+fence.g.v   rd rs1 imm12 9..7=5 6..2=0x0B 1..0=3
+fence.l.cv  rd rs1 imm12 9..7=6 6..2=0x0B 1..0=3
+fence.g.cv  rd rs1 imm12 9..7=7 6..2=0x0B 1..0=3
+
+# vector scalar instructions
+stop    31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3
+utidx   rd       26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3
+movz    rd       rs1      rs2      16..10=0 9..7=5 6..2=0x1D 1..0=3
+movn    rd       rs1      rs2      16..10=1 9..7=5 6..2=0x1D 1..0=3
+fmovz   rd       rs1      rs2      16..10=2 9..7=5 6..2=0x1D 1..0=3
+fmovn   rd       rs1      rs2      16..10=3 9..7=5 6..2=0x1D 1..0=3
+
+ei      rd       26..22=0 21..17=0 16..7=0 6..2=0x1E 1..0=3
+di      rd       26..22=0 21..17=0 16..7=1 6..2=0x1E 1..0=3
+mfpcr   rd       26..22=0 rs2      16..7=2 6..2=0x1E 1..0=3
+mtpcr   31..27=0 rs1      rs2      16..7=3 6..2=0x1E 1..0=3
+eret    31..27=0 26..22=0 21..17=0 16..7=4 6..2=0x1E 1..0=3
+cflush  31..27=0 26..22=0 21..17=0 16..7=5 6..2=0x1E 1..0=3
+
+# 0x7C-0x7F are reserved for >32b instructions
+
+fadd.s      rd rs1 rs2      16..12=0    rm      8..7=0 6..2=0x14 1..0=3
+fsub.s      rd rs1 rs2      16..12=1    rm      8..7=0 6..2=0x14 1..0=3
+fmul.s      rd rs1 rs2      16..12=2    rm      8..7=0 6..2=0x14 1..0=3
+fdiv.s      rd rs1 rs2      16..12=3    rm      8..7=0 6..2=0x14 1..0=3
+fsqrt.s     rd rs1 21..17=0 16..12=4    rm      8..7=0 6..2=0x14 1..0=3
+fsgnj.s     rd rs1 rs2      16..12=5    11..9=0 8..7=0 6..2=0x14 1..0=3
+fsgnjn.s    rd rs1 rs2      16..12=6    11..9=0 8..7=0 6..2=0x14 1..0=3
+fsgnjx.s    rd rs1 rs2      16..12=7    11..9=0 8..7=0 6..2=0x14 1..0=3
+
+fadd.d      rd rs1 rs2      16..12=0x0  rm      8..7=1 6..2=0x14 1..0=3
+fsub.d      rd rs1 rs2      16..12=0x1  rm      8..7=1 6..2=0x14 1..0=3
+fmul.d      rd rs1 rs2      16..12=0x2  rm      8..7=1 6..2=0x14 1..0=3
+fdiv.d      rd rs1 rs2      16..12=0x3  rm      8..7=1 6..2=0x14 1..0=3
+fsqrt.d     rd rs1 21..17=0 16..12=0x4  rm      8..7=1 6..2=0x14 1..0=3
+fsgnj.d     rd rs1 rs2      16..12=0x5  11..9=0 8..7=1 6..2=0x14 1..0=3
+fsgnjn.d    rd rs1 rs2      16..12=0x6  11..9=0 8..7=1 6..2=0x14 1..0=3
+fsgnjx.d    rd rs1 rs2      16..12=0x7  11..9=0 8..7=1 6..2=0x14 1..0=3
+
+fcvt.l.s    rd rs1 21..17=0 16..12=0x8  rm      8..7=0 6..2=0x14 1..0=3
+fcvt.lu.s   rd rs1 21..17=0 16..12=0x9  rm      8..7=0 6..2=0x14 1..0=3
+fcvt.w.s    rd rs1 21..17=0 16..12=0xA  rm      8..7=0 6..2=0x14 1..0=3
+fcvt.wu.s   rd rs1 21..17=0 16..12=0xB  rm      8..7=0 6..2=0x14 1..0=3
+
+fcvt.l.d    rd rs1 21..17=0 16..12=0x8  rm      8..7=1 6..2=0x14 1..0=3
+fcvt.lu.d   rd rs1 21..17=0 16..12=0x9  rm      8..7=1 6..2=0x14 1..0=3
+fcvt.w.d    rd rs1 21..17=0 16..12=0xA  rm      8..7=1 6..2=0x14 1..0=3
+fcvt.wu.d   rd rs1 21..17=0 16..12=0xB  rm      8..7=1 6..2=0x14 1..0=3
+
+fcvt.s.l    rd rs1 21..17=0 16..12=0xC  rm      8..7=0 6..2=0x14 1..0=3
+fcvt.s.lu   rd rs1 21..17=0 16..12=0xD  rm      8..7=0 6..2=0x14 1..0=3
+fcvt.s.w    rd rs1 21..17=0 16..12=0xE  rm      8..7=0 6..2=0x14 1..0=3
+fcvt.s.wu   rd rs1 21..17=0 16..12=0xF  rm      8..7=0 6..2=0x14 1..0=3
+
+fcvt.d.l    rd rs1 21..17=0 16..12=0xC  rm      8..7=1 6..2=0x14 1..0=3
+fcvt.d.lu   rd rs1 21..17=0 16..12=0xD  rm      8..7=1 6..2=0x14 1..0=3
+fcvt.d.w    rd rs1 21..17=0 16..12=0xE  rm      8..7=1 6..2=0x14 1..0=3
+fcvt.d.wu   rd rs1 21..17=0 16..12=0xF  rm      8..7=1 6..2=0x14 1..0=3
+
+fcvt.s.d    rd rs1 21..17=0 16..14=0x4 13..12=1 rm 8..7=0 6..2=0x14 1..0=3
+fcvt.d.s    rd rs1 21..17=0 16..14=0x4 13..12=0 rm 8..7=1 6..2=0x14 1..0=3
+
+feq.s     rd rs1 rs2      16..12=0x15 11..9=0 8..7=0 6..2=0x14 1..0=3
+flt.s     rd rs1 rs2      16..12=0x16 11..9=0 8..7=0 6..2=0x14 1..0=3
+fle.s     rd rs1 rs2      16..12=0x17 11..9=0 8..7=0 6..2=0x14 1..0=3
+
+feq.d     rd rs1 rs2      16..12=0x15 11..9=0 8..7=1 6..2=0x14 1..0=3
+flt.d     rd rs1 rs2      16..12=0x16 11..9=0 8..7=1 6..2=0x14 1..0=3
+fle.d     rd rs1 rs2      16..12=0x17 11..9=0 8..7=1 6..2=0x14 1..0=3
+
+fmin.s    rd rs1 rs2      16..12=0x18 11..9=0 8..7=0 6..2=0x14 1..0=3
+fmax.s    rd rs1 rs2      16..12=0x19 11..9=0 8..7=0 6..2=0x14 1..0=3
+
+fmin.d    rd rs1 rs2      16..12=0x18 11..9=0 8..7=1 6..2=0x14 1..0=3
+fmax.d    rd rs1 rs2      16..12=0x19 11..9=0 8..7=1 6..2=0x14 1..0=3
+
+mftx.s      rd 26..22=0  rs2      16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3
+mftx.d      rd 26..22=0  rs2      16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3
+mffsr       rd 26..22=0  21..17=0 16..12=0x1D 11..9=0 8..7=0 6..2=0x14 1..0=3
+mxtf.s      rd       rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3
+mxtf.d      rd       rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3
+mtfsr       rd       rs1 21..17=0 16..12=0x1F 11..9=0 8..7=0 6..2=0x14 1..0=3
+
+flw        rd rs1 imm12 9..7=2 6..2=0x01 1..0=3
+fld        rd rs1 imm12 9..7=3 6..2=0x01 1..0=3
+
+fsw        imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x09 1..0=3
+fsd        imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x09 1..0=3
+
+fmadd.s     rd rs1 rs2 rs3 rm 8..7=0 6..2=0x10 1..0=3
+fmsub.s     rd rs1 rs2 rs3 rm 8..7=0 6..2=0x11 1..0=3
+fnmsub.s    rd rs1 rs2 rs3 rm 8..7=0 6..2=0x12 1..0=3
+fnmadd.s    rd rs1 rs2 rs3 rm 8..7=0 6..2=0x13 1..0=3
+
+fmadd.d     rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3
+fmsub.d     rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3
+fnmsub.d    rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3
+fnmadd.d    rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3
+
+# vector load mem instructions
+
+#                                                                3=d
+#                                         2=seg                  2=w
+#                                         1=st    1=seg 1=f  1=s 1=h
+#                                         0=u     0=etc 0=x  0=u 0=b
+#           ----------------------------------------------------------------------------
+#                           mem  padding  type     seg  x/f  u/s width  opcode
+# unit stride               |    |        |        |    |    |   |      |
+# xloads                    |    |        |        |    |    |   |      |
+vld         rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
+vlw         rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
+vlwu        rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
+vlh         rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
+vlhu        rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
+vlb         rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
+vlbu        rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
+# floads
+vfld        rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
+vflw        rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+
+#                           mem  padding  type     seg  x/f  u/s width  opcode
+# stride                    |    |        |        |    |    |   |      |
+# xloads                    |    |        |        |    |    |   |      |
+vlstd       rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
+vlstw       rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
+vlstwu      rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
+vlsth       rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
+vlsthu      rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
+vlstb       rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
+vlstbu      rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
+# floads
+vflstd      rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
+vflstw      rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+
+#                           mem  padding  type     seg  x/f  u/s width  opcode
+# segment                   |    |        |        |    |    |   |      |
+# xloads                    |    |        |        |    |    |   |      |
+vlsegd      rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
+vlsegw      rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
+vlsegwu     rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
+vlsegh      rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
+vlseghu     rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
+vlsegb      rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
+vlsegbu     rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
+# floads
+vflsegd     rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
+vflsegw     rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+
+#                                                  seg  x/f  u/s width  opcode
+# stride segment                                   |    |    |   |      |
+# xloads                                           |    |    |   |      |
+vlsegstd    rd rs1 rs2      rs3                    11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3
+vlsegstw    rd rs1 rs2      rs3                    11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3
+vlsegstwu   rd rs1 rs2      rs3                    11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3
+vlsegsth    rd rs1 rs2      rs3                    11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3
+vlsegsthu   rd rs1 rs2      rs3                    11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3
+vlsegstb    rd rs1 rs2      rs3                    11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3
+vlsegstbu   rd rs1 rs2      rs3                    11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3
+# floads
+vflsegstd   rd rs1 rs2      rs3                    11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3
+vflsegstw   rd rs1 rs2      rs3                    11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+
+# vector store mem instructions
+#                           mem  padding  type     seg  x/f  u/s width  opcode
+# unit stride               |    |        |        |    |    |   |      |
+# xstores                   |    |        |        |    |    |   |      |
+vsd         rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
+vsw         rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
+vsh         rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
+vsb         rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
+# fstores
+vfsd        rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
+vfsw        rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+
+#                           mem  padding  type     seg  x/f  u/s width  opcode
+# stride                    |    |        |        |    |    |   |      |
+# xstores                   |    |        |        |    |    |   |      |
+vsstd       rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
+vsstw       rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
+vssth       rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
+vsstb       rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
+# fstores
+vfsstd      rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
+vfsstw      rd rs1 rs2      16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+
+#                           mem  padding  type     seg  x/f  u/s width  opcode
+# segment                   |    |        |        |    |    |   |      |
+# xstores                   |    |        |        |    |    |   |      |
+vssegd      rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
+vssegw      rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
+vssegh      rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
+vssegb      rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
+# fstores
+vfssegd     rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
+vfssegw     rd rs1 rs2      16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+
+#                                                  seg  x/f  u/s width  opcode
+# stride segment                                   |    |    |   |      |
+# xstores                                          |    |    |   |      |
+vssegstd    rd rs1 rs2      rs3                    11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3
+vssegstw    rd rs1 rs2      rs3                    11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3
+vssegsth    rd rs1 rs2      rs3                    11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3
+vssegstb    rd rs1 rs2      rs3                    11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3
+# fstores
+vfssegstd   rd rs1 rs2      rs3                    11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3
+vfssegstw   rd rs1 rs2      rs3                    11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+
+# other vector register instructions
+vmvv        rd       rs1 21..17=0                  16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3
+vmsv        rd       rs1 21..17=0                  16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3
+vmst        rd       rs1 rs2                       16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3
+vmts        rd       rs1 rs2                       16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3
+vfmvv       rd       rs1 21..17=0                  16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3
+vfmsv       rd       rs1 21..17=0                  16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3
+vfmst       rd       rs1 rs2                       16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3
+vfmts       rd       rs1 rs2                       16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3
+
+# other vector immediate instructions
+vvcfgivl    rd       rs1 imm12                               9..8=0 7=1 6..2=0x1C 1..0=3
+vtcfgivl    rd       rs1 imm12                               9..8=1 7=1 6..2=0x1C 1..0=3
+vsetvl      rd       rs1 21..10=0                            9..8=2 7=1 6..2=0x1C 1..0=3
+vf          31..27=0 rs1 imm12                               9..8=3 7=1 6..2=0x1C 1..0=3
+
+# compressed instructions
+c.li      cimm6    crd   4..0=0
+c.addi    cimm6    crd   4..0=1
+c.addiw   cimm6    crd   4..0=29
+c.ldsp    cimm6    crd   4..0=4
+c.lwsp    cimm6    crd   4..0=5
+c.sdsp    cimm6    crd   4..0=6
+c.swsp    cimm6    crd   4..0=8
+
+c.lw0 15=0 crs1    crd   4..0=18
+c.ld0 15=1 crs1    crd   4..0=18
+c.add 15=0 crs1    crd   4..0=26
+c.sub 15=1 crs1    crd   4..0=26
+c.move 15=0 crs1   crd   4..0=2
+
+c.j    15=1   cimm10     4..0=2
+
+c.ld   crds  crs1s cimm5 4..0=9
+c.lw   crds  crs1s cimm5 4..0=10
+c.sd   crs2s crs1s cimm5 4..0=12
+c.sw   crs2s crs1s cimm5 4..0=13
+c.beq  crs2s crs1s cimm5 4..0=16
+c.bne  crs2s crs1s cimm5 4..0=17
+c.flw  crds  crs1s cimm5 4..0=20
+c.fld  crds  crs1s cimm5 4..0=21
+c.fsw  crs2s crs1s cimm5 4..0=22
+c.fsd  crs2s crs1s cimm5 4..0=24
+
+c.slli   crds 12..10=0 cimm5 4..0=25
+c.slli32 crds 12..10=1 cimm5 4..0=25
+c.srli   crds 12..10=2 cimm5 4..0=25
+c.srli32 crds 12..10=3 cimm5 4..0=25
+c.srai   crds 12..10=4 cimm5 4..0=25
+c.srai32 crds 12..10=5 cimm5 4..0=25
+c.slliw  crds 12..10=6 cimm5 4..0=25
+
+c.add3 crds crs1s 9..8=0 crs2bs 4..0=28
+c.sub3 crds crs1s 9..8=1 crs2bs 4..0=28
+c.or3  crds crs1s 9..8=2 crs2bs 4..0=28
+c.and3 crds crs1s 9..8=3 crs2bs 4..0=28
diff --git a/parse-opcodes b/parse-opcodes
new file mode 100755
index 0000000..26b8779
--- /dev/null
+++ b/parse-opcodes
@@ -0,0 +1,791 @@
+#!/usr/bin/python
+
+import math
+import sys
+import tokenize
+
+namelist = []
+match = {}
+mask = {}
+arguments = {}
+types = {}
+
+arglut = {}
+arglut['rd'] = (31,27)
+arglut['rs1'] = (26,22)
+arglut['rs2'] = (21,17)
+arglut['rs3'] = (16,12)
+arglut['rm'] = (11,9)
+arglut['imm25'] = (31,7)
+arglut['imm20'] = (26,7)
+arglut['imm12'] = (21,10)
+arglut['imm12hi'] = (31,27)
+arglut['imm12lo'] = (16,10)
+arglut['shamt'] = (15,10)
+arglut['shamtw'] = (14,10)
+
+arglut['crd'] = (9,5)
+arglut['crs2'] = (9,5)
+arglut['crs1'] = (14,10)
+arglut['crds'] = (15,13)
+arglut['crs2s'] = (15,13)
+arglut['crs2bs'] = (7,5)
+arglut['crs1s'] = (12,10)
+arglut['cimm6'] = (15,10)
+arglut['cimm10'] = (14,5)
+arglut['cimm5'] = (9,5)
+
+typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,,8=r4rm,9=rrm,10=b
+typelut[0x03] = 3
+typelut[0x07] = 3
+typelut[0x13] = 3
+typelut[0x1B] = 3
+typelut[0x23] = 10
+typelut[0x27] = 10
+typelut[0x2B] = 4
+typelut[0x2F] = 4
+typelut[0x33] = 4
+typelut[0x37] = 2
+typelut[0x3B] = 4
+typelut[0x43] = 8
+typelut[0x47] = 8
+typelut[0x4B] = 8
+typelut[0x4F] = 8
+typelut[0x53] = 9
+typelut[0x63] = 10
+typelut[0x67] = 1
+typelut[0x6B] = 3
+typelut[0x6F] = 1
+typelut[0x77] = 4
+typelut[0x7B] = 4
+
+# XXX RVC
+for i in range(0,3):
+  for j in range(0,8):
+    typelut[j*4+i] = 0
+
+# vector opcodes
+typelut[0x0B] = 4
+typelut[0x0F] = 4
+typelut[0x73] = 4
+
+opcode_base = 0
+opcode_size = 7
+funct_base = 7
+funct_size = 3
+
+def binary(n, digits=0):
+  rep = bin(n)[2:]
+  return rep if digits == 0 else ('0' * (digits - len(rep))) + rep
+
+def make_disasm_table(match,mask):
+  print '/* Automatically generated by parse-opcodes */'
+  for name,match in match.iteritems():
+    name2 = name.upper().replace('.','_')
+    print '#define MATCH_%s %s' % (name2, hex(match))
+    print '#define  MASK_%s %s' % (name2, hex(mask[name]))
+
+def make_isasim(match, mask):
+  for name in match.iterkeys():
+    name2 = name.replace('.','_')
+    print 'DECLARE_INSN(%s, 0x%x, 0x%x)' % (name2, match[name], mask[name])
+
+def yank(num,start,len):
+  return (num >> start) & ((1 << len) - 1)
+
+def str_arg(arg0,arg1,match,arguments):
+  if arg0 in arguments:
+    return arg0
+  elif arg1 in arguments:
+    return arg1
+  else:
+    start = arglut[arg0][1]
+    len = arglut[arg0][0] - arglut[arg0][1] + 1
+    return binary(yank(match,start,len),len)
+
+def str_inst(name,arguments):
+  ret = name.upper() + ' '
+  if 'imm12hi' in arguments and 'imm12lo' in arguments:
+    arguments.remove('imm12hi')
+    arguments.remove('imm12lo')
+    arguments.append('imm12')
+  for idx in range(len(arguments)):
+    ret = ret + arguments[idx]
+    if idx != len(arguments)-1:
+      ret = ret + ','
+  ret = ret.replace(',rm','[,rm]')
+  return ret
+
+def print_unimp_type(name,match,arguments):
+  print """
+&
+\\multicolumn{10}{|c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    '0'*32, \
+    'UNIMP' \
+  )
+
+def print_j_type(name,match,arguments):
+  print """
+&
+\\multicolumn{9}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('imm25','',match,arguments), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_lui_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{8}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('rd','',match,arguments), \
+    str_arg('imm20','',match,arguments), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_b_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{4}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('imm12hi','',match,arguments), \
+    str_arg('rs1','',match,arguments), \
+    str_arg('rs2','',match,arguments), \
+    str_arg('imm12lo','',match,arguments), \
+    binary(yank(match,funct_base,funct_size),funct_size), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_i_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{5}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('rd','',match,arguments), \
+    str_arg('rs1','',match,arguments), \
+    str_arg('imm12','',match,arguments), \
+    binary(yank(match,funct_base,funct_size),funct_size), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_ish_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('rd','',match,arguments), \
+    str_arg('rs1','',match,arguments), \
+    binary(yank(match,16,6),6), \
+    str_arg('shamt','',match,arguments), \
+    binary(yank(match,funct_base,funct_size),funct_size), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_ishw_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('rd','',match,arguments), \
+    str_arg('rs1','',match,arguments), \
+    binary(yank(match,15,7),7), \
+    str_arg('shamtw','',match,arguments), \
+    binary(yank(match,funct_base,funct_size),funct_size), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_r_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{4}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('rd','',match,arguments), \
+    str_arg('rs1','',match,arguments), \
+    str_arg('rs2','',match,arguments), \
+    binary(yank(match,10,7),7), \
+    binary(yank(match,funct_base,funct_size),funct_size), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_r4_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('rd','',match,arguments), \
+    str_arg('rs1','',match,arguments), \
+    str_arg('rs2','',match,arguments), \
+    str_arg('rs3','',match,arguments), \
+    binary(yank(match,7,5),5), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_r_rm_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('rd','',match,arguments), \
+    str_arg('rs1','',match,arguments), \
+    str_arg('rs2','',match,arguments), \
+    binary(yank(match,12,5),5), \
+    str_arg('rm','',match,arguments), \
+    binary(yank(match,7,2),2), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_r4_rm_type(name,match,arguments):
+  print """
+&
+\\multicolumn{1}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
+\\multicolumn{2}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('rd','',match,arguments), \
+    str_arg('rs1','',match,arguments), \
+    str_arg('rs2','',match,arguments), \
+    str_arg('rs3','',match,arguments), \
+    str_arg('rm','',match,arguments), \
+    binary(yank(match,7,2),2), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_header():
+  print """
+\\newpage
+
+\\begin{table}[p]
+\\begin{small}
+\\begin{center}
+\\begin{tabular}{rccccccccccl}
+                &
+\\hspace*{0.6in} &
+\\hspace*{0.3in} &
+\\hspace*{0.1in} &
+\\hspace*{0.1in} &
+\\hspace*{0.2in} &
+\\hspace*{0.2in} &
+\\hspace*{0.1in} &
+\\hspace*{0.3in} &
+\\hspace*{0.3in} &
+\\hspace*{0.3in} \\\\
+                      &
+\\instbitrange{31}{27} &
+\\instbitrange{26}{22} &
+\\instbitrange{21}{17} &
+\\instbit{16} &
+\\instbit{15} &
+\\instbitrange{14}{12} &
+\\instbitrange{11}{10} &
+\\instbit{9} &
+\\instbitrange{8}{7} &
+\\instbitrange{6}{0} \\\\
+\\cline{2-11}
+&
+\\multicolumn{9}{|c|}{jump target} &
+\\multicolumn{1}{c|}{opcode} & J-type \\\\
+\\cline{2-11}
+&
+\\multicolumn{1}{|c|}{rd} &
+\\multicolumn{8}{c|}{LUI-immediate} &
+\\multicolumn{1}{c|}{opcode} & LUI-type \\\\
+\\cline{2-11}
+&
+\\multicolumn{1}{|c|}{rd} &
+\\multicolumn{1}{c|}{rs1} &
+\\multicolumn{1}{c|}{imm[11:7]} &
+\\multicolumn{4}{c|}{imm[6:0]} &
+\\multicolumn{2}{c|}{funct3} &
+\\multicolumn{1}{c|}{opcode} & I-type \\\\
+\\cline{2-11}
+&
+\\multicolumn{1}{|c|}{imm[11:7]} &
+\\multicolumn{1}{c|}{rs1} &
+\\multicolumn{1}{c|}{rs2} &
+\\multicolumn{4}{c|}{imm[6:0]} &
+\\multicolumn{2}{c|}{funct3} &
+\\multicolumn{1}{c|}{opcode} & B-type \\\\
+\\cline{2-11}
+&
+\\multicolumn{1}{|c|}{rd} &
+\\multicolumn{1}{c|}{rs1} &
+\\multicolumn{1}{c|}{rs2} &
+\\multicolumn{6}{c|}{funct10} &
+\\multicolumn{1}{c|}{opcode} & R-type \\\\
+\\cline{2-11}
+&
+\\multicolumn{1}{|c|}{rd} &
+\\multicolumn{1}{c|}{rs1} &
+\\multicolumn{1}{c|}{rs2} &
+\\multicolumn{3}{c|}{rs3} &
+\\multicolumn{3}{c|}{funct5} &
+\\multicolumn{1}{c|}{opcode} & R4-type \\\\
+\\cline{2-11}
+  """
+
+def print_subtitle(title):
+  print """
+&
+\\multicolumn{10}{c}{} & \\\\
+&
+\\multicolumn{10}{c}{\\bf %s} & \\\\
+\\cline{2-11}
+  """ % title
+
+def print_footer(caption):
+  print """
+\\end{tabular}
+\\end{center}
+\\end{small}
+%s
+\\label{instr-table}
+\\end{table}
+  """ % (caption and '\\caption{Instruction listing for RISC-V}' or '')
+
+def print_insts(opcode,name,type,min,max):
+  for n in namelist:
+    if yank(match[n],opcode_base,opcode_size) == opcode or n == name:
+      if type == -1 or types[n] == type:
+        if types[n] == 0:
+          print_unimp_type(n,match[n],arguments[n])
+        elif types[n] == 1:
+          print_j_type(n,match[n],arguments[n])
+        elif types[n] == 2:
+          print_lui_type(n,match[n],arguments[n])
+        elif types[n] == 3:
+          print_i_type(n,match[n],arguments[n])
+        elif types[n] == 4 \
+          and (min == -1 or yank(match[n],5,10) >= min) \
+          and (max == -1 or yank(match[n],5,10) <= max):
+          print_r_type(n,match[n],arguments[n])
+        elif types[n] == 5:
+          print_r4_type(n,match[n],arguments[n])
+        elif types[n] == 6:
+          print_ish_type(n,match[n],arguments[n])
+        elif types[n] == 7:
+          print_ishw_type(n,match[n],arguments[n])
+        elif types[n] == 8:
+          print_r4_rm_type(n,match[n],arguments[n])
+        elif types[n] == 9:
+          print_r_rm_type(n,match[n],arguments[n])
+        elif types[n] == 10:
+          print_b_type(n,match[n],arguments[n])
+
+def make_latex_table():
+  print_header()
+  print_subtitle('Unimplemented Instruction')
+  print_insts(0x00,'',-1,-1,-1)
+  print_subtitle('Control Transfer Instructions')
+  print_insts(0x67,'',-1,-1,-1)
+  print_insts(0x6f,'',-1,-1,-1)
+  print_insts(0x63,'',-1,-1,-1)
+  print_insts(0x6b,'',-1,-1,-1)
+  print_subtitle('Memory Instructions')
+  print_insts(0x03,'',-1,-1,-1)
+  print_insts(0x23,'',-1,-1,-1)
+  print_subtitle('Atomic Memory Instructions')
+  print_insts(0x2b,'',-1,-1,-1)
+  print_footer(0)
+
+  print_header()
+  print_subtitle('Integer Compute Instructions')
+  print_insts(0x13,'',-1,-1,-1)
+  print_insts(0x33,'',-1,-1,-1)
+  print_insts(0x37,'',-1,-1,-1)
+  print_subtitle('32-bit Integer Compute Instructions')
+  print_insts(0x1b,'',-1,-1,-1)
+  print_insts(0x3b,'',-1,-1,-1)
+  print_footer(0)
+
+  print_header()
+  print_subtitle('Floating-Point Memory Instructions')
+  print_insts(0x07,'',-1,-1,-1)
+  print_insts(0x27,'',-1,-1,-1)
+  print_subtitle('Floating-Point Compute Instructions')
+  print_insts(-1,'fadd.s',-1,-1,-1)
+  print_insts(-1,'fsub.s',-1,-1,-1)
+  print_insts(-1,'fmul.s',-1,-1,-1)
+  print_insts(-1,'fdiv.s',-1,-1,-1)
+  print_insts(-1,'fsqrt.s',-1,-1,-1)
+  print_insts(-1,'fmin.s',-1,-1,-1)
+  print_insts(-1,'fmax.s',-1,-1,-1)
+  print_insts(-1,'fadd.d',-1,-1,-1)
+  print_insts(-1,'fsub.d',-1,-1,-1)
+  print_insts(-1,'fmul.d',-1,-1,-1)
+  print_insts(-1,'fdiv.d',-1,-1,-1)
+  print_insts(-1,'fsqrt.d',-1,-1,-1)
+  print_insts(-1,'fmin.d',-1,-1,-1)
+  print_insts(-1,'fmax.d',-1,-1,-1)
+  print_insts(-1,'fmadd.s',-1,-1,-1)
+  print_insts(-1,'fmsub.s',-1,-1,-1)
+  print_insts(-1,'fnmsub.s',-1,-1,-1)
+  print_insts(-1,'fnmadd.s',-1,-1,-1)
+  print_insts(-1,'fmadd.d',-1,-1,-1)
+  print_insts(-1,'fmsub.d',-1,-1,-1)
+  print_insts(-1,'fnmsub.d',-1,-1,-1)
+  print_insts(-1,'fnmadd.d',-1,-1,-1)
+  print_footer(0)
+
+  print_header()
+  print_subtitle('Floating-Point Move \& Conversion Instructions')
+  print_insts(-1,'fsgnj.s',-1,-1,-1)
+  print_insts(-1,'fsgnjn.s',-1,-1,-1)
+  print_insts(-1,'fsgnjx.s',-1,-1,-1)
+  print_insts(-1,'fsgnj.d',-1,-1,-1)
+  print_insts(-1,'fsgnjn.d',-1,-1,-1)
+  print_insts(-1,'fsgnjx.d',-1,-1,-1)
+  print_insts(-1,'fcvt.s.d',-1,-1,-1)
+  print_insts(-1,'fcvt.d.s',-1,-1,-1)
+  print_subtitle('Integer to Floating-Point Move \& Conversion Instructions')
+  print_insts(-1,'fcvt.s.l',-1,-1,-1)
+  print_insts(-1,'fcvt.s.lu',-1,-1,-1)
+  print_insts(-1,'fcvt.s.w',-1,-1,-1)
+  print_insts(-1,'fcvt.s.wu',-1,-1,-1)
+  print_insts(-1,'fcvt.d.l',-1,-1,-1)
+  print_insts(-1,'fcvt.d.lu',-1,-1,-1)
+  print_insts(-1,'fcvt.d.w',-1,-1,-1)
+  print_insts(-1,'fcvt.d.wu',-1,-1,-1)
+  print_insts(-1,'mxtf.s',-1,-1,-1)
+  print_insts(-1,'mxtf.d',-1,-1,-1)
+  print_insts(-1,'mtfsr',-1,-1,-1)
+  print_subtitle('Floating-Point to Integer Move \& Conversion Instructions')
+  print_insts(-1,'fcvt.l.s',-1,-1,-1)
+  print_insts(-1,'fcvt.lu.s',-1,-1,-1)
+  print_insts(-1,'fcvt.w.s',-1,-1,-1)
+  print_insts(-1,'fcvt.wu.s',-1,-1,-1)
+  print_insts(-1,'fcvt.l.d',-1,-1,-1)
+  print_insts(-1,'fcvt.lu.d',-1,-1,-1)
+  print_insts(-1,'fcvt.w.d',-1,-1,-1)
+  print_insts(-1,'fcvt.wu.d',-1,-1,-1)
+  print_insts(-1,'mftx.s',-1,-1,-1)
+  print_insts(-1,'mftx.d',-1,-1,-1)
+  print_insts(-1,'mffsr',-1,-1,-1)
+  print_footer(0)
+
+  print_header()
+  print_subtitle('Floating-Point Compare Instructions')
+  print_insts(-1,'feq.s',-1,-1,-1)
+  print_insts(-1,'flt.s',-1,-1,-1)
+  print_insts(-1,'fle.s',-1,-1,-1)
+  print_insts(-1,'feq.d',-1,-1,-1)
+  print_insts(-1,'flt.d',-1,-1,-1)
+  print_insts(-1,'fle.d',-1,-1,-1)
+  print_subtitle('Miscellaneous Memory Instructions')
+  print_insts(0x2f,'',-1,-1,-1)
+  print_subtitle('System Instructions')
+  print_insts(0x77,'',-1,-1,-1)
+  print_footer(1)
+
+def str_verilog_arg(arg0,arg1,match,arguments):
+  if arg0 in arguments:
+    return '?' * (arglut[arg0][0] - arglut[arg0][1] + 1)
+  elif arg1 in arguments:
+    return '?' * (arglut[arg0][0] - arglut[arg0][1] + 1)
+  else:
+    start = arglut[arg0][1]
+    len = arglut[arg0][0] - arglut[arg0][1] + 1
+    return binary(yank(match,start,len),len)
+
+def print_verilog_unimp_type(name,match,arguments):
+  print "`define %-10s 32'b%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    '0'*32 \
+  )
+
+def print_verilog_j_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('imm25','',match,arguments), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_lui_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('rd','',match,arguments), \
+    str_verilog_arg('imm20','',match,arguments), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_b_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('imm12hi','',match,arguments), \
+    str_verilog_arg('rs1','',match,arguments), \
+    str_verilog_arg('rs2','',match,arguments), \
+    str_verilog_arg('imm12lo','',match,arguments), \
+    binary(yank(match,7,3),3), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_i_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('rd','',match,arguments), \
+    str_verilog_arg('rs1','',match,arguments), \
+    str_verilog_arg('imm12','',match,arguments), \
+    binary(yank(match,7,3),3), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_ish_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('rd','',match,arguments), \
+    str_verilog_arg('rs1','',match,arguments), \
+    binary(yank(match,16,6),6), \
+    str_verilog_arg('shamt','',match,arguments), \
+    binary(yank(match,7,3),3), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_ishw_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s_0_%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('rd','',match,arguments), \
+    str_verilog_arg('rs1','',match,arguments), \
+    binary(yank(match,16,6),6), \
+    str_verilog_arg('shamtw','',match,arguments), \
+    binary(yank(match,7,3),3), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_r4_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('rd','',match,arguments), \
+    str_verilog_arg('rs1','',match,arguments), \
+    str_verilog_arg('rs2','',match,arguments), \
+    str_verilog_arg('rs3','',match,arguments), \
+    binary(yank(match,9,3),3), \
+    binary(yank(match,7,2),2), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_r4_rm_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('rd','',match,arguments), \
+    str_verilog_arg('rs1','',match,arguments), \
+    str_verilog_arg('rs2','',match,arguments), \
+    str_verilog_arg('rs3','',match,arguments), \
+    str_verilog_arg('rm','',match,arguments), \
+    binary(yank(match,7,2),2), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_r_rm_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('rd','',match,arguments), \
+    str_verilog_arg('rs1','',match,arguments), \
+    str_verilog_arg('rs2','',match,arguments), \
+    binary(yank(match,12,5),5), \
+    str_verilog_arg('rm','',match,arguments), \
+    binary(yank(match,7,2),2), \
+    binary(yank(match,0,7),7) \
+  )
+
+def print_verilog_r_type(name,match,arguments):
+  print "`define %-10s 32'b%s_%s_%s_%s_%s" % \
+  ( \
+    name.replace('.','_').upper(), \
+    str_verilog_arg('rd','',match,arguments), \
+    str_verilog_arg('rs1','',match,arguments), \
+    str_verilog_arg('rs2','',match,arguments), \
+    binary(yank(match,7,10),10), \
+    binary(yank(match,0,7),7) \
+  )
+
+def make_verilog():
+  print '/* Automatically generated by parse-opcodes */'
+  for name in namelist:
+    if types[name] == 0:
+      print_verilog_unimp_type(name,match[name],arguments[name])
+    elif types[name] == 1:
+      print_verilog_j_type(name,match[name],arguments[name])
+    elif types[name] == 2:
+      print_verilog_lui_type(name,match[name],arguments[name])
+    elif types[name] == 3:
+      print_verilog_i_type(name,match[name],arguments[name])
+    elif types[name] == 4:
+      print_verilog_r_type(name,match[name],arguments[name])
+    elif types[name] == 5:
+      print_verilog_r4_type(name,match[name],arguments[name])
+    elif types[name] == 6:
+      print_verilog_ish_type(name,match[name],arguments[name])
+    elif types[name] == 7:
+      print_verilog_ishw_type(name,match[name],arguments[name])
+    elif types[name] == 8:
+      print_verilog_r4_rm_type(name,match[name],arguments[name])
+    elif types[name] == 9:
+      print_verilog_r_rm_type(name,match[name],arguments[name])
+    elif types[name] == 10:
+      print_verilog_b_type(name,match[name],arguments[name])
+
+for line in sys.stdin:
+  line = line.partition('#')
+  tokens = line[0].split()
+
+  if len(tokens) == 0:
+    continue
+  assert len(tokens) >= 2
+
+  name = tokens[0]
+  mymatch = 0
+  mymask = 0
+  cover = 0
+
+  if not name in arguments.keys():
+    arguments[name] = []
+
+  for token in tokens[1:]:
+    if len(token.split('=')) == 2:
+      tmp = token.split('=')
+      val = int(tmp[1],0)
+      if len(tmp[0].split('..')) == 2:
+        tmp = tmp[0].split('..')
+        hi = int(tmp[0])
+        lo = int(tmp[1])
+        if hi <= lo:
+          sys.exit("%s: bad range %d..%d" % (name,hi,lo))
+      else:
+        hi = lo = int(tmp[0])
+      if val >= (1 << (hi-lo+1)):
+        sys.exit("%s: bad value %d for range %d..%d" % (name,val,hi,lo))
+      mymatch = mymatch | (val << lo)
+      mymask = mymask | ((1<<(hi+1))-(1<<lo))
+      if cover & ((1<<(hi+1))-(1<<lo)):
+        sys.exit("%s: overspecified" % name)
+      cover = cover | ((1<<(hi+1))-(1<<lo))
+    elif token in arglut:
+      if cover & ((1<<(arglut[token][0]+1))-(1<<arglut[token][1])):
+        sys.exit("%s: overspecified" % name)
+      cover = cover | ((1<<(arglut[token][0]+1))-(1<<arglut[token][1]))
+
+      arguments[name].append(token)
+    else:
+      sys.exit("%s: unknown token %s" % (name,token))
+
+  if not (cover == 0xFFFFFFFF or cover == 0xFFFF):
+    sys.exit("%s: not all bits are covered" % name)
+
+  for name2,match2 in match.iteritems():
+    if (match2 & mymask) == mymatch:
+      sys.exit("%s and %s overlap" % (name,name2))
+
+  mask[name] = mymask
+  match[name] = mymatch
+  types[name] = typelut[yank(mymatch,0,7)]
+  if 'shamtw' in arguments[name]:
+    types[name] = 7
+  elif 'imm12' in arguments[name]:
+    types[name] = 3
+  elif 'shamt' in arguments[name]:
+    types[name] = 6
+  elif types[name] == 4 and 'rs3' in arguments[name]:
+    types[name] = 5
+  elif types[name] == 5 and 'rm' in arguments[name]:
+    types[name] = 8
+  elif types[name] == 4 and 'rm' in arguments[name]:
+    types[name] = 9
+  elif name == 'vsetvl':
+    types[name] = 3
+
+  namelist.append(name)
+
+if sys.argv[1] == '-tex':
+  make_latex_table()
+elif sys.argv[1] == '-verilog':
+  make_verilog()
+elif sys.argv[1] == '-disasm':
+  make_disasm_table(match,mask)
+elif sys.argv[1] == '-isasim':
+  make_isasim(match,mask)
+else:
+  assert 0