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* [opcodes,pk,sim,xcc] flip fields to favor little endianGravatar Yunsup Lee2011-01-03
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* [opcodes, pk, sim, xcc] Tweaked FP encodingGravatar Andrew Waterman2010-11-21
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* [opcodes] generate latex and verilog correctlyGravatar Andrew Waterman2010-11-21
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* [xcc, sim, pk, opcodes] new instruction encoding!Gravatar Andrew Waterman2010-11-21
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* [opcodes, pk, sim, xcc] made jumps shorter and PC-relativeGravatar Andrew Waterman2010-11-21
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* [opcodes] add latex table for rm stuffGravatar Yunsup Lee2010-10-31
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* [opcodes] remove .swp fileGravatar Yunsup Lee2010-10-26
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* [sim,xcc,pk,opcodes] static rounding modes for FP insnsGravatar Andrew Waterman2010-10-25
| | | | | | Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
* [opcodes] changed formatting of optab section headersGravatar Andrew Waterman2010-10-20
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* [pk, sim] added FPU emulation support to proxy kernelGravatar Andrew Waterman2010-10-15
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* [xcc] modified opcodes for better FP decode mappingGravatar Andrew Waterman2010-10-07
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* [opcodes] added code field back to syscall/breakGravatar Andrew Waterman2010-10-05
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* [opcodes] updated parse-opcodes for latex tablesGravatar Yunsup Lee2010-10-05
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* [opcodes] update parse-opcodesGravatar Yunsup Lee2010-10-05
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* [xcc, sim] mff now uses rs2 for dataGravatar Andrew Waterman2010-10-02
| | | | this is symmetric with fp stores, so we only need one decoding pipe
* [opcodes, sim, xcc] added mffl.d instructionGravatar Andrew Waterman2010-09-28
| | | | ...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
* [xcc, sim] changed instruction format so imm12 subs for rs2Gravatar Andrew Waterman2010-09-20
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* [xcc, sim] replaced ble/bleu with bge/bgeuGravatar Andrew Waterman2010-09-13
| | | | This will simplify control logic (since every branch has a logical inverse)
* [opcodes] fixed tex table for ish,ishw typesGravatar Yunsup Lee2010-09-12
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* [opcodes] change rsh to ish typesGravatar Yunsup Lee2010-09-12
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* [opcodes] fixed verilog generation for ish,ishw typesGravatar Yunsup Lee2010-09-12
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* [sim] renamed sllv to sll (same for other shifts)Gravatar Andrew Waterman2010-09-12
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* [xcc, sim] moved shamt field and renamed shiftsGravatar Andrew Waterman2010-09-12
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* [xcc, sim] branches now are next-PC-based, not PC-basedGravatar Andrew Waterman2010-09-12
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* add -verilog optionGravatar Yunsup Lee2010-09-12
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* [sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bitGravatar Andrew Waterman2010-09-10
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* [opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)Gravatar Yunsup Lee2010-09-10
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* [opcodes] latex table generation added, new opcode mappingGravatar Yunsup Lee2010-09-10
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* [opcodes,sim,xcc] move opcodes for 3 source instructionsGravatar Yunsup Lee2010-09-09
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* Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"Gravatar Andrew Waterman2010-09-09
| | | | | | | | | | | This reverts commit bf5406d4df625678bc6ec20ce1d48541541dba54. We found a clever way to efficiently implement slti/sltiu despite the reversed operands. The trick is because of the following fact: (a < b) === !(b <= a) === !(b-1 < a) So just turn off the carry-in when doing the subtraction for the comparison.
* [xcc, sim] added slei/sleui in lieu of slti/sltiuGravatar Andrew Waterman2010-09-07
| | | | | Rationale was that since we have the datapath for rc = (ra < rb), it's straightforward to also add rc = !(imm < rb) = (rb <= imm).
* [sim, xcc] bthread threading model exposed; insn encoding cleaned upGravatar Andrew Waterman2010-09-06
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* [sim] added atomic memory operationsGravatar Andrew Waterman2010-09-06
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* [xcc,sim] added fused multiply-add and its cousinsGravatar Andrew Waterman2010-08-22
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* [xcc,sim] Eliminated slori instructionGravatar Andrew Waterman2010-08-22
| | | | | | the "li" macro in RISC-V assembly isn't as efficient anymore for 64b constants, and "la" doesn't work for 64b addresses with ".set noat". But it's worth it to remove an ugly instruction.
* [xcc,sim] implement FP using softfloatGravatar Andrew Waterman2010-08-09
| | | | The intersection of the Hauser FP and MIPS FP is implemented.
* [sim,xcc] Added first few Hauser FP insns (sign-injection)Gravatar Andrew Waterman2010-08-05
| | | | Also updated FPmove test case to test negation and moving between FP regs
* [xcc] Removed ctc1, cfc1 instructions; added fp move test caseGravatar Andrew Waterman2010-08-04
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* [xcc,pk,sim] Added first part of FP supportGravatar Andrew Waterman2010-08-04
| | | | In particular, FP loads, stores, and moves now work.
* [sim,xcc] removed sll32/srl32/sra32 opcodesGravatar Andrew Waterman2010-08-03
| | | | | These instructions handled static shift amounts >= 32. Since we have a 6-bit shift amount field, these opcodes are no longer necessary.
* [pk,sim,xcc] Renamed instructions to RISC-V specGravatar Andrew Waterman2010-08-03
| | | | | | | All word-sized arithmetic operations are now postfixed with 'w', and all double-word-sized arithmetic operations are no longer prefixed with 'd'. mtc0/mfc0 are removed and replaced with mfpcr/mtpcr/mwfpcr/mwtpcr.
* [sim,xcc] Changed instruction format to RISC-VGravatar Andrew Waterman2010-07-28
| | | | | Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes.
* Reorganized directory structureGravatar Andrew Waterman2010-07-18
Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/
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