diff options
| author |  Yunsup Lee <yunsup@cs.berkeley.edu> | 2010-09-12 19:26:33 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2010-09-12 19:44:15 -0700 |
| commit | 7ac50f34b0b163efa9fdadc836cffb4b97b24074 (patch) | |
| tree | b15d689dfa0b1484eccf1ee472108b8f8a2087f4 | |
| parent | 4599bddadd22fde723da3ce11e0c0b6772d76398 (diff) | |
[opcodes] fixed verilog generation for ish,ishw types
| -rw-r--r-- | inst.v | 12 | ||||
| -rwxr-xr-x | parse-opcodes | 16 |
2 files changed, 14 insertions, 14 deletions
@@ -14,9 +14,9 @@ `define ANDI 32'b1110100_?????_?????_100_???????????? `define ORI 32'b1110100_?????_?????_101_???????????? `define XORI 32'b1110100_?????_?????_110_???????????? -`define SLLI 32'b1110100_00000_?????_1110_??????_00000 -`define SRLI 32'b1110100_00000_?????_1110_??????_00000 -`define SRAI 32'b1110100_00000_?????_1110_??????_00000 +`define SLLI 32'b1110100_?????_?????_110000010_?????? +`define SRLI 32'b1110100_?????_?????_110000100_?????? +`define SRAI 32'b1110100_?????_?????_110000110_?????? `define ADD 32'b1110101_?????_?????_0000000000_????? `define SUB 32'b1110101_?????_?????_0000000001_????? `define SLT 32'b1110101_?????_?????_0000000010_????? @@ -36,9 +36,9 @@ `define REM 32'b1110101_?????_?????_0010000110_????? `define REMU 32'b1110101_?????_?????_0010000111_????? `define ADDIW 32'b1110110_?????_?????_000_???????????? -`define SLLIW 32'b1110110_00000_?????_1110_0_?????_00000 -`define SRLIW 32'b1110110_00000_?????_1110_0_?????_00000 -`define SRAIW 32'b1110110_00000_?????_1110_0_?????_00000 +`define SLLIW 32'b1110110_?????_?????_110000010_0_????? +`define SRLIW 32'b1110110_?????_?????_110000100_0_????? +`define SRAIW 32'b1110110_?????_?????_110000110_0_????? `define ADDW 32'b1110111_?????_?????_0000000000_????? `define SUBW 32'b1110111_?????_?????_0000000001_????? `define SLLW 32'b1110111_?????_?????_1110000010_????? diff --git a/parse-opcodes b/parse-opcodes index 4e56615..39f8b89 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -498,25 +498,25 @@ def print_verilog_i_type(name,match,arguments): ) def print_verilog_rsh_type(name,match,arguments): - print "`define %-10s 32'b%s_00000_%s_%s_%s_%s" % \ + print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ + str_verilog_arg('xa','',match,arguments), \ str_verilog_arg('xb','',match,arguments), \ - binary(yank(match,11,4),4), \ - str_verilog_arg('shamt','',match,arguments), \ - str_verilog_arg('xc','',match,arguments) \ + binary(yank(match,5,9),9), \ + str_verilog_arg('shamt','',match,arguments) \ ) def print_verilog_rshw_type(name,match,arguments): - print "`define %-10s 32'b%s_00000_%s_%s_0_%s_%s" % \ + print "`define %-10s 32'b%s_%s_%s_%s_0_%s" % \ ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ + str_verilog_arg('xa','',match,arguments), \ str_verilog_arg('xb','',match,arguments), \ - binary(yank(match,11,4),4), \ - str_verilog_arg('shamtw','',match,arguments), \ - str_verilog_arg('xc','',match,arguments) \ + binary(yank(match,5,9),9), \ + str_verilog_arg('shamtw','',match,arguments) \ ) def print_verilog_r4_type(name,match,arguments): |