Commit message (Collapse) | Author | Age | |
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* | Add referenced/dirty bits to PTE | 2015-03-12 | |
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* | Update to new privileged spec | 2015-03-12 | |
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* | update location of headers for new ABI/toolchain | 2014-12-14 | |
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* | Revert "Enable the four custom instructions" | 2014-11-22 | |
| | | | | | | This reverts commit 70b52dd5fa74b5968a20ded22df4ae3a9a76d7f4. Refactoring support for custom instructions. | ||
* | Merge branch 'pr/1' | 2014-10-24 | |
|\ | | | | | | | | | Conflicts: Makefile | ||
* | | Prevent regenerating the Hwacha spike header by default | 2014-10-23 | |
| | | | | | | | | | | | | Not every instruction in the main opcodes file is implemented by Hwacha; at present, updating opcodes_hwacha_ut.h requires manual culling of the unneeded instructions to avoid breaking the spike build. | ||
| * | Enable the four custom instructions | 2014-10-23 | |
|/ | | | | | | | | Will update encoding.h in the following components: * riscv-isa-sim * riscv-pk * riscv-test-env | ||
* | Move stats register | 2014-04-03 | |
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* | Add hwacha spike header file target | 2014-04-03 | |
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* | Add rdcycleh etc. for RV32 | 2014-03-18 | |
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* | Fix syntax error in generated opcodes | 2014-03-11 | |
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* | New FP encoding | 2014-03-11 | |
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* | Add fclass.{s|d} instructions | 2014-03-06 | |
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* | add hwacha vfmsv instructions | 2014-03-02 | |
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* | Renumber uarch CSRs into custom CSR space | 2014-02-14 | |
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* | Reserve 16 uarch-specific read-only userspace counters | 2014-02-06 | |
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* | Add vfmvv, vfmsv instructions, remove vsetprec | 2014-02-03 | |
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* | Add DECLARE_CAUSE macro | 2014-01-21 | |
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* | Move microthread-specific opcodes to opcodes-hwacha-ut | 2014-01-21 | |
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* | Auto-generate exception cause numbers | 2014-01-21 | |
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* | Merge branch 'confprec' | 2014-01-20 | |
|\ | | | | | | | | | Conflicts: Makefile | ||
* | | swap JAL/JALR again | 2014-01-13 | |
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* | | New RDCYCLE encoding | 2013-12-09 | |
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| * | Add vsetprec instruction | 2013-11-29 | |
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* | | New privileged ISA | 2013-11-25 | |
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| * | Merge branch 'master' into confprec | 2013-11-24 | |
| |\ | |/ |/| | | | | | Conflicts: Makefile | ||
| * | Add line in Makefile to parse confprec | 2013-11-24 | |
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* | | add missing imm for stores | 2013-11-22 | |
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* | | fix slli/slliw encoding bug | 2013-11-21 | |
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* | | changes to the instr-table | 2013-10-29 | |
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| * | Move half-precision opcodes to opcodes-hwacha-ut | 2013-10-27 | |
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| * | Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprec | 2013-10-27 | |
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* | | add gitignore | 2013-10-18 | |
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| * | Add half-precision floating-point instructions | 2013-10-17 | |
|/ | | | | * Add opcodes-hwacha-pseudo to be produced as well, or else GCC will complain. | ||
* | add hwacha exception support | 2013-10-17 | |
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* | custom-1 opcodes are now 0x0A | 2013-10-17 | |
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* | revamp hwacha-v3 opcodes | 2013-10-10 | |
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* | Fix funct field in tables. | 2013-09-21 | |
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* | Remove old file | 2013-09-21 | |
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* | Update ISA encoding | 2013-09-21 | |
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* | hwacha v3: inst format follows the new rocket accelerator extensions | 2013-08-07 | |
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* | Rename MTFSR/MFFSR to FSSR/FRSR | 2013-08-06 | |
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* | Add custom opcode space | 2013-08-06 | |
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* | HW ignores upper bits of fence, but SW supplies 0 | 2013-07-31 | |
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* | Swap J and JALR encodings | 2013-07-31 | |
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* | change supervisor encoding | 2013-07-26 | |
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* | tweaks | 2013-07-26 | |
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* | Factor out Hwacha/RVC and rename MFTX/MXTF to FMV | 2013-07-26 | |
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* | Refactor parse-opcodes | 2013-07-25 | |
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* | Remove JALR static hints | 2013-07-25 | |
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