Merge branch 'master' into confprec

Conflicts:
	Makefile

5 files changed, 100 insertions, 59 deletions

diff --git a/Makefile b/Makefile
index 3092932..95f7d76 100644
--- a/Makefile
+++ b/Makefile
@@ -14,11 +14,11 @@ $(PK_H): opcodes parse-opcodes
 
 $(GAS_H): opcodes opcodes-hwacha opcodes-hwacha-ut opcodes-rvc opcodes-custom opcodes-hwacha-pseudo parse-opcodes
 	./parse-opcodes -disasm < $< > $@
+	./parse-opcodes -disasm < opcodes-rvc >> $@
+	./parse-opcodes -disasm < opcodes-custom >> $@
 	./parse-opcodes -disasm < opcodes-hwacha >> $@
 	./parse-opcodes -disasm < opcodes-hwacha-pseudo >> $@
 	./parse-opcodes -disasm < opcodes-hwacha-ut >> $@
-	./parse-opcodes -disasm < opcodes-rvc >> $@
-	./parse-opcodes -disasm < opcodes-custom >> $@
 
 $(XCC_H): opcodes parse-opcodes
 	./parse-opcodes -disasm < $< > $@
diff --git a/inst.chisel b/inst.chisel
index b77863a..abda1c6 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -10,7 +10,7 @@
   def LUI                = Bits("b?????????????????????????0110111")
   def AUIPC              = Bits("b?????????????????????????0010111")
   def ADDI               = Bits("b?????????????????000?????0010011")
-  def SLLI               = Bits("b010000???????????001?????0010011")
+  def SLLI               = Bits("b000000???????????001?????0010011")
   def SLTI               = Bits("b?????????????????010?????0010011")
   def SLTIU              = Bits("b?????????????????011?????0010011")
   def XORI               = Bits("b?????????????????100?????0010011")
@@ -37,7 +37,7 @@
   def REM                = Bits("b0000001??????????110?????0110011")
   def REMU               = Bits("b0000001??????????111?????0110011")
   def ADDIW              = Bits("b?????????????????000?????0011011")
-  def SLLIW              = Bits("b0100000??????????001?????0011011")
+  def SLLIW              = Bits("b0000000??????????001?????0011011")
   def SRLIW              = Bits("b0000000??????????101?????0011011")
   def SRAIW              = Bits("b0100000??????????101?????0011011")
   def ADDW               = Bits("b0000000??????????000?????0111011")
diff --git a/instr-table.tex b/instr-table.tex
index 3893683..70d5157 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -4,13 +4,15 @@
 \begin{table}[p]
 \begin{small}
 \begin{center}
-\begin{tabular}{rccccccccccl}
+\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
+& & & & & & & & & & \\
                       &
 \multicolumn{1}{l}{\instbit{31}} &
 \multicolumn{1}{r}{\instbit{27}} &
 \instbit{26} &
 \instbit{25} &
-\multicolumn{2}{c}{\instbitrange{24}{20}} &
+\multicolumn{1}{l}{\instbit{24}} &
+\multicolumn{1}{r}{\instbit{20}} &
 \instbitrange{19}{15} &
 \instbitrange{14}{12} &
 \instbitrange{11}{7} &
@@ -41,18 +43,18 @@
 \multicolumn{4}{|c|}{imm[11:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{imm[4:0]} &
 \multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{imm[4:0]} &
 \multicolumn{1}{c|}{opcode} & S-type \\
 \cline{2-11}
 
 
 &
-\multicolumn{4}{|c|}{imm[12, 10:5]} &
+\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{imm[4:1, 11]} &
+\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
 \multicolumn{1}{c|}{opcode} & SB-type \\
 \cline{2-11}
 
@@ -65,7 +67,7 @@
 
 
 &
-\multicolumn{8}{|c|}{imm[20, 10:1, 11, 19:12]} &
+\multicolumn{8}{|c|}{imm[20$\vert$10:1$\vert$11$\vert$19:12]} &
 \multicolumn{1}{c|}{rd} &
 \multicolumn{1}{c|}{opcode} & UJ-type \\
 \cline{2-11}
@@ -93,7 +95,7 @@
   
 
 &
-\multicolumn{8}{|c|}{imm[20, 10:1, 11, 19:12]} &
+\multicolumn{8}{|c|}{imm[20$\vert$10:1$\vert$11$\vert$19:12]} &
 \multicolumn{1}{c|}{rd} &
 \multicolumn{1}{c|}{1100111} & JAL rd,imm \\
 \cline{2-11}
@@ -109,61 +111,61 @@
   
 
 &
-\multicolumn{4}{|c|}{imm[12, 10:5]} &
+\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{imm[4:1, 11]} &
+\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
 \multicolumn{1}{c|}{1100011} & BEQ rs1,rs2,imm \\
 \cline{2-11}
   
 
 &
-\multicolumn{4}{|c|}{imm[12, 10:5]} &
+\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{imm[4:1, 11]} &
+\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
 \multicolumn{1}{c|}{1100011} & BNE rs1,rs2,imm \\
 \cline{2-11}
   
 
 &
-\multicolumn{4}{|c|}{imm[12, 10:5]} &
+\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{100} &
-\multicolumn{1}{c|}{imm[4:1, 11]} &
+\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
 \multicolumn{1}{c|}{1100011} & BLT rs1,rs2,imm \\
 \cline{2-11}
   
 
 &
-\multicolumn{4}{|c|}{imm[12, 10:5]} &
+\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{imm[4:1, 11]} &
+\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
 \multicolumn{1}{c|}{1100011} & BGE rs1,rs2,imm \\
 \cline{2-11}
   
 
 &
-\multicolumn{4}{|c|}{imm[12, 10:5]} &
+\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{110} &
-\multicolumn{1}{c|}{imm[4:1, 11]} &
+\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
 \multicolumn{1}{c|}{1100011} & BLTU rs1,rs2,imm \\
 \cline{2-11}
   
 
 &
-\multicolumn{4}{|c|}{imm[12, 10:5]} &
+\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{111} &
-\multicolumn{1}{c|}{imm[4:1, 11]} &
+\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
 \multicolumn{1}{c|}{1100011} & BGEU rs1,rs2,imm \\
 \cline{2-11}
   
@@ -219,7 +221,7 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{000} &
 \multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100011} & SB rs1,rs2 \\
+\multicolumn{1}{c|}{0100011} & SB rs1,rs2,imm \\
 \cline{2-11}
   
 
@@ -229,7 +231,7 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{001} &
 \multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100011} & SH rs1,rs2 \\
+\multicolumn{1}{c|}{0100011} & SH rs1,rs2,imm \\
 \cline{2-11}
   
 
@@ -239,7 +241,7 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100011} & SW rs1,rs2 \\
+\multicolumn{1}{c|}{0100011} & SW rs1,rs2,imm \\
 \cline{2-11}
   
 
@@ -298,7 +300,7 @@
   
 
 &
-\multicolumn{3}{|c|}{010000} &
+\multicolumn{3}{|c|}{000000} &
 \multicolumn{3}{c|}{shamt} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{001} &
@@ -428,8 +430,8 @@
   
 
 &
-\multicolumn{1}{|c|}{0000} &
-\multicolumn{4}{c|}{~~~pred~~~~} &
+\multicolumn{2}{|c|}{0000} &
+\multicolumn{3}{c|}{pred} &
 \multicolumn{1}{c|}{succ} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{000} &
@@ -439,8 +441,8 @@
   
 
 &
-\multicolumn{1}{|c|}{0000} &
-\multicolumn{4}{c|}{0000} &
+\multicolumn{2}{|c|}{0000} &
+\multicolumn{3}{c|}{0000} &
 \multicolumn{1}{c|}{0000} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{001} &
@@ -512,13 +514,15 @@
 \begin{table}[p]
 \begin{small}
 \begin{center}
-\begin{tabular}{rccccccccccl}
+\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
+& & & & & & & & & & \\
                       &
 \multicolumn{1}{l}{\instbit{31}} &
 \multicolumn{1}{r}{\instbit{27}} &
 \instbit{26} &
 \instbit{25} &
-\multicolumn{2}{c}{\instbitrange{24}{20}} &
+\multicolumn{1}{l}{\instbit{24}} &
+\multicolumn{1}{r}{\instbit{20}} &
 \instbitrange{19}{15} &
 \instbitrange{14}{12} &
 \instbitrange{11}{7} &
@@ -549,8 +553,8 @@
 \multicolumn{4}{|c|}{imm[11:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{imm[4:0]} &
 \multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{imm[4:0]} &
 \multicolumn{1}{c|}{opcode} & S-type \\
 \cline{2-11}
 
@@ -586,7 +590,7 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{011} &
 \multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100011} & SD rs1,rs2 \\
+\multicolumn{1}{c|}{0100011} & SD rs1,rs2,imm \\
 \cline{2-11}
   
 
@@ -600,7 +604,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0100000} &
+\multicolumn{4}{|c|}{0000000} &
 \multicolumn{2}{c|}{shamt} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{001} &
@@ -975,13 +979,15 @@
 \begin{table}[p]
 \begin{small}
 \begin{center}
-\begin{tabular}{rccccccccccl}
+\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
+& & & & & & & & & & \\
                       &
 \multicolumn{1}{l}{\instbit{31}} &
 \multicolumn{1}{r}{\instbit{27}} &
 \instbit{26} &
 \instbit{25} &
-\multicolumn{2}{c}{\instbitrange{24}{20}} &
+\multicolumn{1}{l}{\instbit{24}} &
+\multicolumn{1}{r}{\instbit{20}} &
 \instbitrange{19}{15} &
 \instbitrange{14}{12} &
 \instbitrange{11}{7} &
@@ -1000,6 +1006,17 @@
 
 
 &
+\multicolumn{2}{|c|}{rs3} &
+\multicolumn{2}{c|}{funct2} &
+\multicolumn{2}{c|}{rs2} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{opcode} & R4-type \\
+\cline{2-11}
+  
+
+&
 \multicolumn{6}{|c|}{imm[11:0]} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{funct3} &
@@ -1012,8 +1029,8 @@
 \multicolumn{4}{|c|}{imm[11:5]} &
 \multicolumn{2}{c|}{rs2} &
 \multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{imm[4:0]} &
 \multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{imm[4:0]} &
 \multicolumn{1}{c|}{opcode} & S-type \\
 \cline{2-11}
 
@@ -1179,7 +1196,7 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100111} & FSW rs1,rs2 \\
+\multicolumn{1}{c|}{0100111} & FSW rs1,rs2,imm \\
 \cline{2-11}
   
 
@@ -1450,13 +1467,15 @@
 \begin{table}[p]
 \begin{small}
 \begin{center}
-\begin{tabular}{rccccccccccl}
+\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
+& & & & & & & & & & \\
                       &
 \multicolumn{1}{l}{\instbit{31}} &
 \multicolumn{1}{r}{\instbit{27}} &
 \instbit{26} &
 \instbit{25} &
-\multicolumn{2}{c}{\instbitrange{24}{20}} &
+\multicolumn{1}{l}{\instbit{24}} &
+\multicolumn{1}{r}{\instbit{20}} &
 \instbitrange{19}{15} &
 \instbitrange{14}{12} &
 \instbitrange{11}{7} &
@@ -1486,6 +1505,25 @@
   
 
 &
+\multicolumn{6}{|c|}{imm[11:0]} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{opcode} & I-type \\
+\cline{2-11}
+
+
+&
+\multicolumn{4}{|c|}{imm[11:5]} &
+\multicolumn{2}{c|}{rs2} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{imm[4:0]} &
+\multicolumn{1}{c|}{opcode} & S-type \\
+\cline{2-11}
+
+
+&
 \multicolumn{10}{c}{} & \\
 &
 \multicolumn{10}{c}{\bf RV64F Standard Extension (in addition to RV32F)} & \\
@@ -1554,7 +1592,7 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{011} &
 \multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100111} & FSD rs1,rs2 \\
+\multicolumn{1}{c|}{0100111} & FSD rs1,rs2,imm \\
 \cline{2-11}
   
 
diff --git a/opcodes b/opcodes
index e0f087b..c0405b7 100644
--- a/opcodes
+++ b/opcodes
@@ -22,7 +22,7 @@ lui     rd imm20 6..2=0x0D 1..0=3
 auipc   rd imm20 6..2=0x05 1..0=3
 
 addi    rd rs1 imm12           14..12=0 6..2=0x04 1..0=3
-slli    rd rs1 31..26=16 shamt 14..12=1 6..2=0x04 1..0=3
+slli    rd rs1 31..26=0  shamt 14..12=1 6..2=0x04 1..0=3
 slti    rd rs1 imm12           14..12=2 6..2=0x04 1..0=3
 sltiu   rd rs1 imm12           14..12=3 6..2=0x04 1..0=3
 xori    rd rs1 imm12           14..12=4 6..2=0x04 1..0=3
@@ -52,7 +52,7 @@ rem     rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3
 remu    rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3
 
 addiw   rd rs1 imm12            14..12=0 6..2=0x06 1..0=3
-slliw   rd rs1 31..25=32 shamtw 14..12=1 6..2=0x06 1..0=3
+slliw   rd rs1 31..25=0  shamtw 14..12=1 6..2=0x06 1..0=3
 srliw   rd rs1 31..25=0  shamtw 14..12=5 6..2=0x06 1..0=3
 sraiw   rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3
 
diff --git a/parse-opcodes b/parse-opcodes
index d46861d..3117b8e 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -77,6 +77,7 @@ def str_inst(name,arguments):
   if 'imm12hi' in arguments and 'imm12lo' in arguments:
     arguments.remove('imm12hi')
     arguments.remove('imm12lo')
+    arguments.append('imm')
   if 'bimm12hi' in arguments and 'bimm12lo' in arguments:
     arguments.remove('bimm12hi')
     arguments.remove('bimm12lo')
@@ -140,7 +141,7 @@ def print_uj_type(name,match,arguments):
 \\cline{2-11}
   """ % \
   ( \
-    str_arg('jimm20','imm[20, 10:1, 11, 19:12]',match,arguments), \
+    str_arg('jimm20','imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]',match,arguments), \
     str_arg('rd','',match,arguments), \
     binary(yank(match,opcode_base,opcode_size),opcode_size), \
     str_inst(name,arguments) \
@@ -179,11 +180,11 @@ def print_sb_type(name,match,arguments):
 \\cline{2-11}
   """ % \
   ( \
-    str_arg('bimm12hi','imm[12, 10:5]',match,arguments), \
+    str_arg('bimm12hi','imm[12$\\vert$10:5]',match,arguments), \
     str_arg('rs2','',match,arguments), \
     str_arg('rs1','',match,arguments), \
     binary(yank(match,funct_base,funct_size),funct_size), \
-    str_arg('bimm12lo','imm[4:1, 11]',match,arguments), \
+    str_arg('bimm12lo','imm[4:1$\\vert$11]',match,arguments), \
     binary(yank(match,opcode_base,opcode_size),opcode_size), \
     str_inst(name,arguments) \
   )
@@ -319,8 +320,8 @@ def print_amo_type(name,match,arguments):
 def print_fence_type(name,match,arguments):
   print """
 &
-\\multicolumn{1}{|c|}{%s} &
-\\multicolumn{4}{c|}{%s} &
+\\multicolumn{2}{|c|}{%s} &
+\\multicolumn{3}{c|}{%s} &
 \\multicolumn{1}{c|}{%s} &
 \\multicolumn{1}{c|}{%s} &
 \\multicolumn{1}{c|}{%s} &
@@ -330,7 +331,7 @@ def print_fence_type(name,match,arguments):
   """ % \
   ( \
     binary(yank(match,28,4),4), \
-    str_arg('pred','~~~pred~~~~',match,arguments), \
+    str_arg('pred','pred',match,arguments), \
     str_arg('succ','',match,arguments), \
     str_arg('rs1','',match,arguments), \
     binary(yank(match,funct_base,funct_size),funct_size), \
@@ -346,13 +347,15 @@ def print_header(*types):
 \\begin{table}[p]
 \\begin{small}
 \\begin{center}
-\\begin{tabular}{rccccccccccl}
+\\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
+& & & & & & & & & & \\\\
                       &
 \\multicolumn{1}{l}{\\instbit{31}} &
 \\multicolumn{1}{r}{\\instbit{27}} &
 \\instbit{26} &
 \\instbit{25} &
-\\multicolumn{2}{c}{\\instbitrange{24}{20}} &
+\\multicolumn{1}{l}{\\instbit{24}} &
+\\multicolumn{1}{r}{\\instbit{20}} &
 \\instbitrange{19}{15} &
 \\instbitrange{14}{12} &
 \\instbitrange{11}{7} &
@@ -398,19 +401,19 @@ def print_header(*types):
 \\multicolumn{4}{|c|}{imm[11:5]} &
 \\multicolumn{2}{c|}{rs2} &
 \\multicolumn{1}{c|}{rs1} &
-\\multicolumn{1}{c|}{imm[4:0]} &
 \\multicolumn{1}{c|}{funct3} &
+\\multicolumn{1}{c|}{imm[4:0]} &
 \\multicolumn{1}{c|}{opcode} & S-type \\\\
 \\cline{2-11}
 """
   if 'sb' in types:
     print """
 &
-\\multicolumn{4}{|c|}{imm[12, 10:5]} &
+\\multicolumn{4}{|c|}{imm[12$\\vert$10:5]} &
 \\multicolumn{2}{c|}{rs2} &
 \\multicolumn{1}{c|}{rs1} &
 \\multicolumn{1}{c|}{funct3} &
-\\multicolumn{1}{c|}{imm[4:1, 11]} &
+\\multicolumn{1}{c|}{imm[4:1$\\vert$11]} &
 \\multicolumn{1}{c|}{opcode} & SB-type \\\\
 \\cline{2-11}
 """
@@ -425,7 +428,7 @@ def print_header(*types):
   if 'uj' in types:
     print """
 &
-\\multicolumn{8}{|c|}{imm[20, 10:1, 11, 19:12]} &
+\\multicolumn{8}{|c|}{imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]} &
 \\multicolumn{1}{c|}{rd} &
 \\multicolumn{1}{c|}{opcode} & UJ-type \\\\
 \\cline{2-11}
@@ -507,7 +510,7 @@ def make_latex_table():
   print_insts('amomin.w', 'amomax.w', 'amominu.w', 'amomaxu.w')
   print_footer(0)
 
-  print_header('r','a','i','s')
+  print_header('r','r4','i','s')
   print_subtitle('RV64A Standard Extension (in addition to RV32A)')
   print_insts('lr.d', 'sc.d')
   print_insts('amoswap.d')
@@ -524,7 +527,7 @@ def make_latex_table():
   print_insts('fssr', 'frsr')
   print_footer(0)
 
-  print_header('r','r4')
+  print_header('r','r4','i','s')
   print_subtitle('RV64F Standard Extension (in addition to RV32F)')
   print_insts('fcvt.s.l', 'fcvt.s.lu')
   print_insts('fcvt.l.s', 'fcvt.lu.s')