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authorGravatar Stephen Twigg <sdtwigg@eecs.berkeley.edu>2014-04-03 16:20:28 -0700
committerGravatar Stephen Twigg <sdtwigg@eecs.berkeley.edu>2014-04-03 16:20:28 -0700
commit16237298565dc2aec4d153b81581649e5485490c (patch)
tree53d42afb4500e5067f40dcd92409d3354ebc086d
parent89daf14d5b338c2d603a76477dfdbe8211b5aac0 (diff)
Add hwacha spike header file target
-rw-r--r--Makefile11
1 files changed, 10 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index 4bc2d18..6c84f92 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,5 @@
ISASIM_H := ../riscv-isa-sim/riscv/encoding.h
+ISASIM_HWACHA_H := ../riscv-isa-sim/hwacha/opcodes_hwacha_ut.h
PK_H := ../riscv-pk/pk/encoding.h
ENV_H := ../riscv-tests/env/encoding.h
GAS_H := ../riscv-gcc/binutils-2.21.1/include/opcode/riscv-opc.h
@@ -6,7 +7,7 @@ XCC_H := ../riscv-gcc/gcc-4.6.1/gcc/config/riscv/riscv-opc.h
ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom
-install: $(ISASIM_H) $(PK_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex
+install: $(ISASIM_H) $(ISASIM_HWACHA_H) $(PK_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex
$(ISASIM_H) $(PK_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes
cp encoding.h $@
@@ -15,6 +16,14 @@ $(ISASIM_H) $(PK_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes
$(GAS_H) $(XCC_H): $(ALL_OPCODES) parse-opcodes
cat $(ALL_OPCODES) | ./parse-opcodes -c > $@
+$(ISASIM_HWACHA_H): $(ALL_OPCODES) parse-opcodes
+ echo "#define DECLARE_INSN DECLARE_INSN" > hwacha.tmp.cc
+ cat opcodes opcodes-hwacha-ut | ./parse-opcodes -c >> hwacha.tmp.cc
+ sed -i -e 's/DECLARE_INSN(/DECLARE_INSN(ut_/g' hwacha.tmp.cc
+ gcc -E -P hwacha.tmp.cc -o $@
+ sort $@ -o $@ # Sorted to make culling unneeded instructions easier
+ rm -f hwacha.tmp.cc
+
inst.chisel: $(ALL_OPCODES) parse-opcodes
cat opcodes opcodes-custom | ./parse-opcodes -chisel > $@