Add rdcycleh etc. for RV32

4 files changed, 90 insertions, 45 deletions

diff --git a/inst.chisel b/inst.chisel
index efb1ba7..455ca08 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -255,6 +255,10 @@ object CSRs {
   val uarch13 = 0xccd
   val uarch14 = 0xcce
   val uarch15 = 0xccf
+  val counth = 0x586
+  val cycleh = 0xc80
+  val timeh = 0xc81
+  val instreth = 0xc82
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
     res += fflags
@@ -301,4 +305,12 @@ object CSRs {
     res += uarch15
     res.toArray
   }
+  val all32 = {
+    val res = collection.mutable.ArrayBuffer(all:_*)
+    res += counth
+    res += cycleh
+    res += timeh
+    res += instreth
+    res.toArray
+  }
 }
diff --git a/instr-table.tex b/instr-table.tex
index 3e881ea..bb5fe1b 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -452,8 +452,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00000} &
+\multicolumn{6}{|c|}{000000000000} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{000} &
 \multicolumn{1}{c|}{00000} &
@@ -462,8 +461,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00001} &
+\multicolumn{6}{|c|}{000000000001} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{000} &
 \multicolumn{1}{c|}{00000} &
@@ -472,8 +470,7 @@
   
 
 &
-\multicolumn{4}{|c|}{1100000} &
-\multicolumn{2}{c|}{00000} &
+\multicolumn{6}{|c|}{110000000000} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -482,8 +479,16 @@
   
 
 &
-\multicolumn{4}{|c|}{1100000} &
-\multicolumn{2}{c|}{00001} &
+\multicolumn{6}{|c|}{110010000000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{010} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{1110011} & RDCYCLEH rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{6}{|c|}{110000000001} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -492,8 +497,16 @@
   
 
 &
-\multicolumn{4}{|c|}{1100000} &
-\multicolumn{2}{c|}{00010} &
+\multicolumn{6}{|c|}{110010000001} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{010} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{1110011} & RDTIMEH rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{6}{|c|}{110000000010} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -501,6 +514,15 @@
 \cline{2-11}
   
 
+&
+\multicolumn{6}{|c|}{110010000010} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{010} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{1110011} & RDINSTRETH rd \\
+\cline{2-11}
+  
+
 \end{tabular}
 \end{center}
 \end{small}
@@ -1475,8 +1497,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00011} &
+\multicolumn{6}{|c|}{000000000011} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -1485,8 +1506,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00010} &
+\multicolumn{6}{|c|}{000000000010} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -1495,8 +1515,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00001} &
+\multicolumn{6}{|c|}{000000000001} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -1505,8 +1524,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00011} &
+\multicolumn{6}{|c|}{000000000011} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{001} &
 \multicolumn{1}{c|}{rd} &
@@ -1515,8 +1533,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00010} &
+\multicolumn{6}{|c|}{000000000010} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{001} &
 \multicolumn{1}{c|}{rd} &
@@ -1525,8 +1542,7 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00001} &
+\multicolumn{6}{|c|}{000000000001} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{001} &
 \multicolumn{1}{c|}{rd} &
@@ -1535,9 +1551,8 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00010} &
-\multicolumn{1}{c|}{imm[4:0]} &
+\multicolumn{6}{|c|}{000000000010} &
+\multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{101} &
 \multicolumn{1}{c|}{rd} &
 \multicolumn{1}{c|}{1110011} & FSRMI rd,imm \\
@@ -1545,9 +1560,8 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00001} &
-\multicolumn{1}{c|}{imm[4:0]} &
+\multicolumn{6}{|c|}{000000000001} &
+\multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{101} &
 \multicolumn{1}{c|}{rd} &
 \multicolumn{1}{c|}{1110011} & FSFLAGSI rd,imm \\
diff --git a/opcodes-pseudo b/opcodes-pseudo
index ba28d72..4171e7e 100644
--- a/opcodes-pseudo
+++ b/opcodes-pseudo
@@ -4,14 +4,17 @@
 @srai.rv32 rd rs1 31..25=32 shamtw  14..12=5 6..2=0x04 1..0=3
 
 # SYSTEM pseudo-instructions that map to csr*
-@frflags   rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3
-@fsflags   rd rs1      31..20=0x001 14..12=1 6..2=0x1C 1..0=3
-@fsflagsi  rd zimm     31..20=0x001 14..12=5 6..2=0x1C 1..0=3
-@frrm      rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3
-@fsrm      rd rs1      31..20=0x002 14..12=1 6..2=0x1C 1..0=3
-@fsrmi     rd zimm     31..20=0x002 14..12=5 6..2=0x1C 1..0=3
-@fscsr     rd rs1      31..20=0x003 14..12=1 6..2=0x1C 1..0=3
-@frcsr     rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3
-@rdcycle   rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3
-@rdtime    rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3
-@rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3
+@frflags    rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3
+@fsflags    rd rs1      31..20=0x001 14..12=1 6..2=0x1C 1..0=3
+@fsflagsi   rd zimm     31..20=0x001 14..12=5 6..2=0x1C 1..0=3
+@frrm       rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3
+@fsrm       rd rs1      31..20=0x002 14..12=1 6..2=0x1C 1..0=3
+@fsrmi      rd zimm     31..20=0x002 14..12=5 6..2=0x1C 1..0=3
+@fscsr      rd rs1      31..20=0x003 14..12=1 6..2=0x1C 1..0=3
+@frcsr      rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3
+@rdcycle    rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3
+@rdtime     rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3
+@rdinstret  rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3
+@rdcycleh   rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3
+@rdtimeh    rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3
+@rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3
diff --git a/parse-opcodes b/parse-opcodes
index 9d43f1d..68b2767 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -101,6 +101,13 @@ csrs = [
   (0xCCF, 'uarch15'),
 ]
 
+csrs32 = [
+  (0x586, 'counth'),
+  (0xC80, 'cycleh'),
+  (0xC81, 'timeh'),
+  (0xC82, 'instreth'),
+]
+
 opcode_base = 0
 opcode_size = 7
 funct_base = 12
@@ -118,7 +125,7 @@ def make_c(match,mask):
     name2 = name.upper().replace('.','_')
     print '#define MATCH_%s %s' % (name2, hex(match[name]))
     print '#define MASK_%s  %s' % (name2, hex(mask[name]))
-  for num, name in csrs:
+  for num, name in csrs+csrs32:
     print '#define CSR_%s %s' % (name.upper(), hex(num))
   for num, name in causes:
     print '#define CAUSE_%s %s' % (name.upper().replace(' ', '_'), hex(num))
@@ -131,12 +138,12 @@ def make_c(match,mask):
   print '#endif'
 
   print '#ifdef DECLARE_CSR'
-  for num, name in csrs:
+  for num, name in csrs+csrs32:
     print 'DECLARE_CSR(%s, CSR_%s)' % (name, name.upper())
   print '#endif'
 
   print '#ifdef DECLARE_CAUSE'
-  for num, name in csrs:
+  for num, name in csrs+csrs32:
     print 'DECLARE_CAUSE("%s", CAUSE_%s)' % (name, name.upper().replace(' ', '_'))
   print '#endif'
 
@@ -550,7 +557,7 @@ def print_inst(n):
     print_u_type(n, match[n], arguments[n])
   elif 'jimm20' in arguments[n]:
     print_uj_type(n, match[n], arguments[n])
-  elif 'imm12' in arguments[n]:
+  elif 'imm12' in arguments[n] or (match[n] & 0x7f) == (match['scall'] & 0x7f):
     print_i_type(n, match[n], arguments[n])
   elif 'imm12hi' in arguments[n]:
     print_s_type(n, match[n], arguments[n])
@@ -574,7 +581,10 @@ def make_latex_table():
   print_insts('addi', 'slti', 'sltiu', 'xori', 'ori', 'andi', 'slli.rv32', 'srli.rv32', 'srai.rv32')
   print_insts('add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and')
   print_insts('fence', 'fence.i')
-  print_insts('scall', 'sbreak', 'rdcycle', 'rdtime', 'rdinstret')
+  print_insts('scall', 'sbreak')
+  print_insts('rdcycle', 'rdcycleh')
+  print_insts('rdtime', 'rdtimeh')
+  print_insts('rdinstret', 'rdinstreth')
   print_footer(0)
 
   print_header('r','a','i','s')
@@ -657,7 +667,7 @@ def make_chisel():
   print '  }'
   print '}'
   print 'object CSRs {'
-  for num, name in csrs:
+  for num, name in csrs+csrs32:
     print '  val %s = %s' % (name, hex(num))
   print '  val all = {'
   print '    val res = collection.mutable.ArrayBuffer[Int]()'
@@ -665,6 +675,12 @@ def make_chisel():
     print '    res += %s' % (name)
   print '    res.toArray'
   print '  }'
+  print '  val all32 = {'
+  print '    val res = collection.mutable.ArrayBuffer(all:_*)'
+  for num, name in csrs32:
+    print '    res += %s' % (name)
+  print '    res.toArray'
+  print '  }'
   print '}'
 
 for line in sys.stdin: