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authorGravatar Yunsup Lee <yunsup@cs.berkeley.edu>2013-11-21 14:40:33 -0800
committerGravatar Yunsup Lee <yunsup@cs.berkeley.edu>2013-11-21 14:40:33 -0800
commite9ad4cabe84d3f235278c8e2f920d9e776db21f7 (patch)
tree6dc92aa845841d3744a31fd57b88e708034a3138
parent2983e55547558ab4ca2865c9ecd517e077695730 (diff)
fix slli/slliw encoding bug
-rw-r--r--Makefile3
-rw-r--r--inst.chisel4
-rw-r--r--instr-table.tex4
-rw-r--r--opcodes4
4 files changed, 8 insertions, 7 deletions
diff --git a/Makefile b/Makefile
index 6034644..c2b134f 100644
--- a/Makefile
+++ b/Makefile
@@ -13,9 +13,10 @@ $(PK_H): opcodes parse-opcodes
$(GAS_H): opcodes opcodes-hwacha opcodes-rvc opcodes-custom parse-opcodes
./parse-opcodes -disasm < $< > $@
- #./parse-opcodes -disasm < opcodes-hwacha >> $@
./parse-opcodes -disasm < opcodes-rvc >> $@
./parse-opcodes -disasm < opcodes-custom >> $@
+ ./parse-opcodes -disasm < opcodes-hwacha >> $@
+ ./parse-opcodes -disasm < opcodes-hwacha-pseudo >> $@
$(XCC_H): opcodes parse-opcodes
./parse-opcodes -disasm < $< > $@
diff --git a/inst.chisel b/inst.chisel
index b77863a..abda1c6 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -10,7 +10,7 @@
def LUI = Bits("b?????????????????????????0110111")
def AUIPC = Bits("b?????????????????????????0010111")
def ADDI = Bits("b?????????????????000?????0010011")
- def SLLI = Bits("b010000???????????001?????0010011")
+ def SLLI = Bits("b000000???????????001?????0010011")
def SLTI = Bits("b?????????????????010?????0010011")
def SLTIU = Bits("b?????????????????011?????0010011")
def XORI = Bits("b?????????????????100?????0010011")
@@ -37,7 +37,7 @@
def REM = Bits("b0000001??????????110?????0110011")
def REMU = Bits("b0000001??????????111?????0110011")
def ADDIW = Bits("b?????????????????000?????0011011")
- def SLLIW = Bits("b0100000??????????001?????0011011")
+ def SLLIW = Bits("b0000000??????????001?????0011011")
def SRLIW = Bits("b0000000??????????101?????0011011")
def SRAIW = Bits("b0100000??????????101?????0011011")
def ADDW = Bits("b0000000??????????000?????0111011")
diff --git a/instr-table.tex b/instr-table.tex
index c6c5ddb..efea3ac 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -300,7 +300,7 @@
&
-\multicolumn{3}{|c|}{010000} &
+\multicolumn{3}{|c|}{000000} &
\multicolumn{3}{c|}{shamt} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{001} &
@@ -604,7 +604,7 @@
&
-\multicolumn{4}{|c|}{0100000} &
+\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{shamt} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{001} &
diff --git a/opcodes b/opcodes
index 44490c5..62efae9 100644
--- a/opcodes
+++ b/opcodes
@@ -22,7 +22,7 @@ lui rd imm20 6..2=0x0D 1..0=3
auipc rd imm20 6..2=0x05 1..0=3
addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3
-slli rd rs1 31..26=16 shamt 14..12=1 6..2=0x04 1..0=3
+slli rd rs1 31..26=0 shamt 14..12=1 6..2=0x04 1..0=3
slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3
sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3
xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3
@@ -52,7 +52,7 @@ rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3
remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3
addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3
-slliw rd rs1 31..25=32 shamtw 14..12=1 6..2=0x06 1..0=3
+slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3
srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3
sraiw rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3