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riscv-opcodes
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RISC-V opcodes
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Commit message (
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Author
Age
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New virtual memory implementation (Sv39)
Andrew Waterman
2015-03-24
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Merge [shm]call into ecall, [shm]ret into eret
Andrew Waterman
2015-03-17
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vxcpthold exposes the first source operand
Yunsup Lee
2015-03-16
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Add hcall instruction
Andrew Waterman
2015-03-12
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Add referenced/dirty bits to PTE
Andrew Waterman
2015-03-12
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Update to new privileged spec
Andrew Waterman
2015-03-12
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update location of headers for new ABI/toolchain
Colin Schmidt
2014-12-14
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Revert "Enable the four custom instructions"
Yunsup Lee
2014-11-22
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Merge branch 'pr/1'
Yunsup Lee
2014-10-24
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Prevent regenerating the Hwacha spike header by default
Albert Ou
2014-10-23
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Enable the four custom instructions
Arun Thomas
2014-10-23
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Move stats register
Stephen Twigg
2014-04-03
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Add hwacha spike header file target
Stephen Twigg
2014-04-03
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Add rdcycleh etc. for RV32
Andrew Waterman
2014-03-18
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Fix syntax error in generated opcodes
Andrew Waterman
2014-03-11
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New FP encoding
Andrew Waterman
2014-03-11
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Add fclass.{s|d} instructions
Andrew Waterman
2014-03-06
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add hwacha vfmsv instructions
Yunsup Lee
2014-03-02
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Renumber uarch CSRs into custom CSR space
Andrew Waterman
2014-02-14
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Reserve 16 uarch-specific read-only userspace counters
Andrew Waterman
2014-02-06
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Add vfmvv, vfmsv instructions, remove vsetprec
Quan Nguyen
2014-02-03
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Add DECLARE_CAUSE macro
Andrew Waterman
2014-01-21
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Move microthread-specific opcodes to opcodes-hwacha-ut
Quan Nguyen
2014-01-21
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Auto-generate exception cause numbers
Andrew Waterman
2014-01-21
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Merge branch 'confprec'
Quan Nguyen
2014-01-20
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swap JAL/JALR again
Andrew Waterman
2014-01-13
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New RDCYCLE encoding
Andrew Waterman
2013-12-09
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Add vsetprec instruction
Quan Nguyen
2013-11-29
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New privileged ISA
Andrew Waterman
2013-11-25
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Merge branch 'master' into confprec
Quan Nguyen
2013-11-24
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Add line in Makefile to parse confprec
Quan Nguyen
2013-11-24
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add missing imm for stores
Yunsup Lee
2013-11-22
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fix slli/slliw encoding bug
Yunsup Lee
2013-11-21
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changes to the instr-table
Yunsup Lee
2013-10-29
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Move half-precision opcodes to opcodes-hwacha-ut
Quan Nguyen
2013-10-27
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Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprec
Quan Nguyen
2013-10-27
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add gitignore
Yunsup Lee
2013-10-18
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Add half-precision floating-point instructions
Quan Nguyen
2013-10-17
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add hwacha exception support
Yunsup Lee
2013-10-17
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custom-1 opcodes are now 0x0A
Yunsup Lee
2013-10-17
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revamp hwacha-v3 opcodes
Yunsup Lee
2013-10-10
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Fix funct field in tables.
Andrew Waterman
2013-09-21
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Remove old file
Andrew Waterman
2013-09-21
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Update ISA encoding
Andrew Waterman
2013-09-21
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hwacha v3: inst format follows the new rocket accelerator extensions
Yunsup Lee
2013-08-07
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Rename MTFSR/MFFSR to FSSR/FRSR
Andrew Waterman
2013-08-06
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Add custom opcode space
Andrew Waterman
2013-08-06
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HW ignores upper bits of fence, but SW supplies 0
Andrew Waterman
2013-07-31
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Swap J and JALR encodings
Andrew Waterman
2013-07-31
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change supervisor encoding
Yunsup Lee
2013-07-26
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