riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
*	Auto-generate exception cause numbers	Andrew Waterman	2014-01-21
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*	Merge branch 'confprec'	Quan Nguyen	2014-01-20
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* \|	swap JAL/JALR again	Andrew Waterman	2014-01-13
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* \|	New RDCYCLE encoding	Andrew Waterman	2013-12-09
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\| *	Add vsetprec instruction	Quan Nguyen	2013-11-29
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* \|	New privileged ISA	Andrew Waterman	2013-11-25
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\| *	Merge branch 'master' into confprec	Quan Nguyen	2013-11-24
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\| *	Add line in Makefile to parse confprec	Quan Nguyen	2013-11-24
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* \|	add missing imm for stores	Yunsup Lee	2013-11-22
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* \|	fix slli/slliw encoding bug	Yunsup Lee	2013-11-21
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* \|	changes to the instr-table	Yunsup Lee	2013-10-29
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\| *	Move half-precision opcodes to opcodes-hwacha-ut	Quan Nguyen	2013-10-27
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\| *	Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprec	Quan Nguyen	2013-10-27
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* \|	add gitignore	Yunsup Lee	2013-10-18
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\| *	Add half-precision floating-point instructions	Quan Nguyen	2013-10-17
\|/ \| \| \|	* Add opcodes-hwacha-pseudo to be produced as well, or else GCC will complain.
*	add hwacha exception support	Yunsup Lee	2013-10-17
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*	custom-1 opcodes are now 0x0A	Yunsup Lee	2013-10-17
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*	revamp hwacha-v3 opcodes	Yunsup Lee	2013-10-10
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*	Fix funct field in tables.	Andrew Waterman	2013-09-21
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*	Remove old file	Andrew Waterman	2013-09-21
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*	Update ISA encoding	Andrew Waterman	2013-09-21
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*	hwacha v3: inst format follows the new rocket accelerator extensions	Yunsup Lee	2013-08-07
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*	Rename MTFSR/MFFSR to FSSR/FRSR	Andrew Waterman	2013-08-06
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*	Add custom opcode space	Andrew Waterman	2013-08-06
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*	HW ignores upper bits of fence, but SW supplies 0	Andrew Waterman	2013-07-31
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*	Swap J and JALR encodings	Andrew Waterman	2013-07-31
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*	change supervisor encoding	Yunsup Lee	2013-07-26
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*	tweaks	Yunsup Lee	2013-07-26
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*	Factor out Hwacha/RVC and rename MFTX/MXTF to FMV	Andrew Waterman	2013-07-26
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*	Refactor parse-opcodes	Andrew Waterman	2013-07-25
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*	Remove JALR static hints	Andrew Waterman	2013-07-25
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*	Remove CFLUSH	Andrew Waterman	2013-07-23
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*	add auipc, lr, sc	Andrew Waterman	2013-04-17
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*	new supervisor mode	Andrew Waterman	2012-03-24
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*	change vector fence names/encoding	Andrew Waterman	2012-03-18
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*	clean up vector exception instructions	Yunsup Lee	2012-03-18
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*	add more instructions for vector exception handling	Yunsup Lee	2012-03-13
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*	add vvcfg,vtcfg	Yunsup Lee	2012-03-13
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*	opcodes cleanup	Yunsup Lee	2012-03-13
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*	slight change to vector supervisor instructions	Yunsup Lee	2012-03-10
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*	new instructions to handle vector exceptions	Yunsup Lee	2012-03-03
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*	temporary undoing of renaming	Andrew Waterman	2011-06-19
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*	Renamed packages	Andrew Waterman	2011-06-19
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*	[riscv-isa-run] code cleanup; added README	Andrew Waterman	2011-06-19
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*	[sim, opcodes] made sim more decoupled from opcodes	Andrew Waterman	2011-06-10
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*	[sim,opcodes] improved sim build and run performance	Andrew Waterman	2011-05-29
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*	[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)	Yunsup Lee	2011-05-18
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*	[opcodes,pk,sim,xcc] resolve a conflict	Yunsup Lee	2011-05-15
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*	[libs,opcodes,pk,sim,xcc] add mov,fmov, shuffle vec insts	Yunsup Lee	2011-05-15
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*	tweaked encoding of rdcycle & cousins	Andrew Waterman	2011-05-13
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