riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
...
*	[xcc,opcodes,pk,sim] krste's re-renaming spree	Andrew Waterman	2011-02-15
\|
*	[xcc,sim,opcodes] removed mtflh/mffl/mffh	Andrew Waterman	2011-02-15
\| \| \| \|	in rv32 these will be replaced with loads and stores.
*	[sim,xcc,opcodes] added back mtflh.d	Andrew Waterman	2011-02-02
\|
*	[opcodes,pk,sim,xcc] synci now bombs whole icache	Andrew Waterman	2011-02-02
\|
*	[xcc,opcodes,pk,sim] cleanup to FP ISA	Andrew Waterman	2011-02-01
\| \| \| \| \| \| \|	- Added 5th rounding mode - Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...) - merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode - made MFFL.D and MFFH.D illegal in RV64
*	[sim,opcodes] add mulhsu instruction	Andrew Waterman	2011-01-25
\|
*	[opcodes,pk,sim,xcc] great renumbering of 2011, part deux	Andrew Waterman	2011-01-25
\|
*	[sim, pk, xcc, opcodes] great instruction renaming of 2011	Andrew Waterman	2011-01-20
\|
*	[opcodes, sim, xcc] made *w insns illegal in RV32	Andrew Waterman	2011-01-18
\| \| \| \|	now generic variants behave differently in RV32 and RV64.
*	[opcodes, pk, sim, xcc] removed nor, normalized macros to addi	Andrew Waterman	2011-01-17
\|
*	[opcodes,pk,sim,xcc] flip fields to favor little endian	Yunsup Lee	2011-01-03
\|
*	[opcodes, pk, sim, xcc] Tweaked FP encoding	Andrew Waterman	2010-11-21
\|
*	[opcodes] generate latex and verilog correctly	Andrew Waterman	2010-11-21
\|
*	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	2010-11-21
\|
*	[opcodes, pk, sim, xcc] made jumps shorter and PC-relative	Andrew Waterman	2010-11-21
\|
*	[opcodes] add latex table for rm stuff	Yunsup Lee	2010-10-31
\|
*	[sim,xcc,pk,opcodes] static rounding modes for FP insns	Andrew Waterman	2010-10-25
\| \| \| \| \| \|	Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
*	[xcc] modified opcodes for better FP decode mapping	Andrew Waterman	2010-10-07
\|
*	[opcodes] added code field back to syscall/break	Andrew Waterman	2010-10-05
\|
*	[xcc, sim] mff now uses rs2 for data	Andrew Waterman	2010-10-02
\| \| \| \|	this is symmetric with fp stores, so we only need one decoding pipe
*	[opcodes, sim, xcc] added mffl.d instruction	Andrew Waterman	2010-09-28
\| \| \| \|	...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
*	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	2010-09-20
\|
*	[xcc, sim] replaced ble/bleu with bge/bgeu	Andrew Waterman	2010-09-13
\| \| \| \|	This will simplify control logic (since every branch has a logical inverse)
*	[sim] renamed sllv to sll (same for other shifts)	Andrew Waterman	2010-09-12
\|
*	[xcc, sim] moved shamt field and renamed shifts	Andrew Waterman	2010-09-12
\|
*	[xcc, sim] branches now are next-PC-based, not PC-based	Andrew Waterman	2010-09-12
\|
*	[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit	Andrew Waterman	2010-09-10
\|
*	[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)	Yunsup Lee	2010-09-10
\|
*	[opcodes] latex table generation added, new opcode mapping	Yunsup Lee	2010-09-10
\|
*	[opcodes,sim,xcc] move opcodes for 3 source instructions	Yunsup Lee	2010-09-09
\|
*	Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"	Andrew Waterman	2010-09-09
\| \| \| \| \| \| \| \| \| \| \|	This reverts commit bf5406d4df625678bc6ec20ce1d48541541dba54. We found a clever way to efficiently implement slti/sltiu despite the reversed operands. The trick is because of the following fact: (a < b) === !(b <= a) === !(b-1 < a) So just turn off the carry-in when doing the subtraction for the comparison.
*	[xcc, sim] added slei/sleui in lieu of slti/sltiu	Andrew Waterman	2010-09-07
\| \| \| \| \|	Rationale was that since we have the datapath for rc = (ra < rb), it's straightforward to also add rc = !(imm < rb) = (rb <= imm).
*	[sim, xcc] bthread threading model exposed; insn encoding cleaned up	Andrew Waterman	2010-09-06
\|
*	[sim] added atomic memory operations	Andrew Waterman	2010-09-06
\|
*	[xcc,sim] added fused multiply-add and its cousins	Andrew Waterman	2010-08-22
\|
*	[xcc,sim] Eliminated slori instruction	Andrew Waterman	2010-08-22
\| \| \| \| \| \|	the "li" macro in RISC-V assembly isn't as efficient anymore for 64b constants, and "la" doesn't work for 64b addresses with ".set noat". But it's worth it to remove an ugly instruction.
*	[xcc,sim] implement FP using softfloat	Andrew Waterman	2010-08-09
\| \| \| \|	The intersection of the Hauser FP and MIPS FP is implemented.
*	[sim,xcc] Added first few Hauser FP insns (sign-injection)	Andrew Waterman	2010-08-05
\| \| \| \|	Also updated FPmove test case to test negation and moving between FP regs
*	[xcc] Removed ctc1, cfc1 instructions; added fp move test case	Andrew Waterman	2010-08-04
\|
*	[xcc,pk,sim] Added first part of FP support	Andrew Waterman	2010-08-04
\| \| \| \|	In particular, FP loads, stores, and moves now work.
*	[sim,xcc] removed sll32/srl32/sra32 opcodes	Andrew Waterman	2010-08-03
\| \| \| \| \|	These instructions handled static shift amounts >= 32. Since we have a 6-bit shift amount field, these opcodes are no longer necessary.
*	[pk,sim,xcc] Renamed instructions to RISC-V spec	Andrew Waterman	2010-08-03
\| \| \| \| \| \| \|	All word-sized arithmetic operations are now postfixed with 'w', and all double-word-sized arithmetic operations are no longer prefixed with 'd'. mtc0/mfc0 are removed and replaced with mfpcr/mtpcr/mwfpcr/mwtpcr.
*	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	2010-07-28
\| \| \| \| \|	Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes.
*	Reorganized directory structure	Andrew Waterman	2010-07-18
	Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/