diff options
| author |  Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-09-06 22:22:09 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-09-06 22:22:09 -0700 |
| commit | 1ea0a57383d9df9ea50fd163d64fb4033b44bb92 (patch) | |
| tree | 81d521a3aa140d22c14831054c2fcef441db5730 /opcodes | |
| parent | a65908611f52bb52c74af6d464ae0d8bc223917c (diff) | |
[sim, xcc] bthread threading model exposed; insn encoding cleaned up
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes | 29 |
1 files changed, 14 insertions, 15 deletions
@@ -106,18 +106,17 @@ jalr.c 31..25=0x7B 19..15=0 14..12=0 11..5=0 ra rc jalr.r 31..25=0x7B 19..15=0 14..12=0 11..5=1 ra rc jalr.j 31..25=0x7B 19..15=0 14..12=0 11..5=2 ra rc rdpc 31..25=0x7B 24..15=0 14..12=1 11..5=0 rc -rdhwr 31..25=0x7B 19..15=0 14..12=2 11..5=0 rc ra -sync 31..25=0x7B 24..15=0 14..12=3 11..0=0 -syscall 31..25=0x7B 24..15=0 14..12=4 11..0=0 -break 31..25=0x7B 24..15=0 14..12=5 11..0=0 - -ei 31..25=0x7E 14..12=0 19..15=0 11..0=0 ra -di 31..25=0x7E 14..12=1 19..15=0 11..0=0 ra +mfcr 31..25=0x7B 24..20=0 14..12=2 11..5=0 rc rb +mtcr 31..25=0x7B 14..12=3 11..0=0 ra rb +sync 31..25=0x7B 24..15=0 14..12=4 11..0=0 +syscall 31..25=0x7B 24..15=0 14..12=5 11..0=0 +break 31..25=0x7B 24..15=0 14..12=6 11..0=0 + +ei 31..25=0x7E 14..12=0 24..15=0 11..5=0 rc +di 31..25=0x7E 14..12=1 24..15=0 11..5=0 rc eret 31..25=0x7E 14..12=2 24..15=0 11..0=0 -mfpcr 31..25=0x7E 14..12=4 11..0=0 ra rb -mwfpcr 31..25=0x7E 14..12=5 11..0=0 ra rb -mtpcr 31..25=0x7E 14..12=6 11..0=0 ra rb -mwtpcr 31..25=0x7E 14..12=7 11..0=0 ra rb +mfpcr 31..25=0x7E 14..12=4 24..20=0 11..5=0 rc rb +mtpcr 31..25=0x7E 14..12=5 11..0=0 ra rb # 0x7F is reserved for 64-bit-long instructions @@ -185,8 +184,8 @@ l.d 31..25=0x69 14..12=3 rb ra imm s.s 31..25=0x69 14..12=6 rb ra imm s.d 31..25=0x69 14..12=7 rb ra imm -mff.s 31..25=0x6A 14..12=0 11..0=0 ra rb -mff.d 31..25=0x6A 14..12=1 11..0=0 ra rb -mtf.s 31..25=0x6A 14..12=4 11..0=0 ra rb -mtf.d 31..25=0x6A 14..12=5 11..0=0 ra rb +mff.s 31..25=0x6A 19..15=0 14..12=0 11..5=0 ra rc +mff.d 31..25=0x6A 19..15=0 14..12=1 11..5=0 ra rc +mtf.s 31..25=0x6A 19..15=0 14..12=4 11..5=0 ra rc +mtf.d 31..25=0x6A 19..15=0 14..12=5 11..5=0 ra rc |