diff options
| author |  Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-03 20:48:02 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-03 20:48:02 -0700 |
| commit | ff4cdc131da26fdd3f0e2e2ec04127e2b55aa4eb (patch) | |
| tree | ca8e34ad10d9a6efc59f07a61cd75fb3ba413399 /opcodes | |
| parent | 056659263eaebb716eee839054e540cb83e3381b (diff) | |
[pk,sim,xcc] Renamed instructions to RISC-V spec
All word-sized arithmetic operations are now postfixed with 'w',
and all double-word-sized arithmetic operations are no longer
prefixed with 'd'. mtc0/mfc0 are removed and replaced with
mfpcr/mtpcr/mwfpcr/mwtpcr.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes | 52 |
1 files changed, 26 insertions, 26 deletions
@@ -22,7 +22,7 @@ ble 31..25=0x73 14..12=4 ra rb imm bleu 31..25=0x73 14..12=5 ra rb imm addi 31..25=0x74 14..12=0 ra rb imm -daddi 31..25=0x74 14..12=1 ra rb imm +addiw 31..25=0x74 14..12=1 ra rb imm slti 31..25=0x74 14..12=2 ra rb imm sltiu 31..25=0x74 14..12=3 ra rb imm andi 31..25=0x74 14..12=4 ra rb imm @@ -50,29 +50,29 @@ sllv 31..25=0x75 14..12=4 11..5=1 rc rb ra srlv 31..25=0x75 14..12=4 11..5=2 rc rb ra srav 31..25=0x75 14..12=4 11..5=3 rc rb ra sll 31..25=0x75 14..12=5 11..10=0 24..20=0 rc rb shamt +sll32 31..25=0x76 14..12=5 11..10=1 24..20=0 rc rb shamt srl 31..25=0x75 14..12=6 11..10=0 24..20=0 rc rb shamt +srl32 31..25=0x76 14..12=6 11..10=1 24..20=0 rc rb shamt sra 31..25=0x75 14..12=7 11..10=0 24..20=0 rc rb shamt - -dadd 31..25=0x76 14..12=0 11..5=0 rc rb ra -dsub 31..25=0x76 14..12=0 11..5=1 rc rb ra - -dmul 31..25=0x76 14..12=1 11..5=0 rc rb ra -dmulh 31..25=0x76 14..12=1 11..5=2 rc rb ra -dmulhu 31..25=0x76 14..12=1 11..5=3 rc rb ra -ddiv 31..25=0x76 14..12=1 11..5=4 rc rb ra -ddivu 31..25=0x76 14..12=1 11..5=5 rc rb ra -drem 31..25=0x76 14..12=1 11..5=6 rc rb ra -dremu 31..25=0x76 14..12=1 11..5=7 rc rb ra - -dsllv 31..25=0x76 14..12=4 11..5=1 rc rb ra -dsrlv 31..25=0x76 14..12=4 11..5=2 rc rb ra -dsrav 31..25=0x76 14..12=4 11..5=3 rc rb ra -dsll 31..25=0x76 14..12=5 11..10=0 24..20=0 rc rb shamt -dsll32 31..25=0x76 14..12=5 11..10=1 24..20=0 rc rb shamt -dsrl 31..25=0x76 14..12=6 11..10=0 24..20=0 rc rb shamt -dsrl32 31..25=0x76 14..12=6 11..10=1 24..20=0 rc rb shamt -dsra 31..25=0x76 14..12=7 11..10=0 24..20=0 rc rb shamt -dsra32 31..25=0x76 14..12=7 11..10=1 24..20=0 rc rb shamt +sra32 31..25=0x76 14..12=7 11..10=1 24..20=0 rc rb shamt + +addw 31..25=0x76 14..12=0 11..5=0 rc rb ra +subw 31..25=0x76 14..12=0 11..5=1 rc rb ra + +mulw 31..25=0x76 14..12=1 11..5=0 rc rb ra +mulhw 31..25=0x76 14..12=1 11..5=2 rc rb ra +mulhuw 31..25=0x76 14..12=1 11..5=3 rc rb ra +divw 31..25=0x76 14..12=1 11..5=4 rc rb ra +divuw 31..25=0x76 14..12=1 11..5=5 rc rb ra +remw 31..25=0x76 14..12=1 11..5=6 rc rb ra +remuw 31..25=0x76 14..12=1 11..5=7 rc rb ra + +sllvw 31..25=0x76 14..12=4 11..5=1 rc rb ra +srlvw 31..25=0x76 14..12=4 11..5=2 rc rb ra +sravw 31..25=0x76 14..12=4 11..5=3 rc rb ra +sllw 31..25=0x76 14..12=5 11..10=0 24..20=0 rc rb shamt +srlw 31..25=0x76 14..12=6 11..10=0 24..20=0 rc rb shamt +sraw 31..25=0x76 14..12=7 11..10=0 24..20=0 rc rb shamt lb 31..25=0x78 14..12=0 rb ra imm lh 31..25=0x78 14..12=1 rb ra imm @@ -105,10 +105,10 @@ break 31..25=0x7B 24..15=0 14..12=5 11..0=0 ei 31..25=0x7E 14..12=0 19..15=0 11..0=0 ra di 31..25=0x7E 14..12=1 19..15=0 11..0=0 ra eret 31..25=0x7E 14..12=2 24..15=0 11..0=0 -mfc0 31..25=0x7E 14..12=4 11..0=0 ra rb -dmfc0 31..25=0x7E 14..12=5 11..0=0 ra rb -mtc0 31..25=0x7E 14..12=6 11..0=0 ra rb -dmtc0 31..25=0x7E 14..12=7 11..0=0 ra rb +mfpcr 31..25=0x7E 14..12=4 11..0=0 ra rb +mwfpcr 31..25=0x7E 14..12=5 11..0=0 ra rb +mtpcr 31..25=0x7E 14..12=6 11..0=0 ra rb +mwtpcr 31..25=0x7E 14..12=7 11..0=0 ra rb # 0x7F is reserved for 64-bit-long instructions |