riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
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*	[xcc, sim] replaced ble/bleu with bge/bgeu	Andrew Waterman	2010-09-13
\| \| \| \|	This will simplify control logic (since every branch has a logical inverse)
*	[opcodes] fixed tex table for ish,ishw types	Yunsup Lee	2010-09-12
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*	[opcodes] change rsh to ish types	Yunsup Lee	2010-09-12
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*	[opcodes] fixed verilog generation for ish,ishw types	Yunsup Lee	2010-09-12
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*	[sim] renamed sllv to sll (same for other shifts)	Andrew Waterman	2010-09-12
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*	[xcc, sim] moved shamt field and renamed shifts	Andrew Waterman	2010-09-12
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*	[xcc, sim] branches now are next-PC-based, not PC-based	Andrew Waterman	2010-09-12
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*	add -verilog option	Yunsup Lee	2010-09-12
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*	[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit	Andrew Waterman	2010-09-10
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*	[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)	Yunsup Lee	2010-09-10
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*	[opcodes] latex table generation added, new opcode mapping	Yunsup Lee	2010-09-10
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*	[opcodes,sim,xcc] move opcodes for 3 source instructions	Yunsup Lee	2010-09-09
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*	Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"	Andrew Waterman	2010-09-09
\| \| \| \| \| \| \| \| \| \| \|	This reverts commit bf5406d4df625678bc6ec20ce1d48541541dba54. We found a clever way to efficiently implement slti/sltiu despite the reversed operands. The trick is because of the following fact: (a < b) === !(b <= a) === !(b-1 < a) So just turn off the carry-in when doing the subtraction for the comparison.
*	[xcc, sim] added slei/sleui in lieu of slti/sltiu	Andrew Waterman	2010-09-07
\| \| \| \| \|	Rationale was that since we have the datapath for rc = (ra < rb), it's straightforward to also add rc = !(imm < rb) = (rb <= imm).
*	[sim, xcc] bthread threading model exposed; insn encoding cleaned up	Andrew Waterman	2010-09-06
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*	[sim] added atomic memory operations	Andrew Waterman	2010-09-06
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*	[xcc,sim] added fused multiply-add and its cousins	Andrew Waterman	2010-08-22
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*	[xcc,sim] Eliminated slori instruction	Andrew Waterman	2010-08-22
\| \| \| \| \| \|	the "li" macro in RISC-V assembly isn't as efficient anymore for 64b constants, and "la" doesn't work for 64b addresses with ".set noat". But it's worth it to remove an ugly instruction.
*	[xcc,sim] implement FP using softfloat	Andrew Waterman	2010-08-09
\| \| \| \|	The intersection of the Hauser FP and MIPS FP is implemented.
*	[sim,xcc] Added first few Hauser FP insns (sign-injection)	Andrew Waterman	2010-08-05
\| \| \| \|	Also updated FPmove test case to test negation and moving between FP regs
*	[xcc] Removed ctc1, cfc1 instructions; added fp move test case	Andrew Waterman	2010-08-04
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*	[xcc,pk,sim] Added first part of FP support	Andrew Waterman	2010-08-04
\| \| \| \|	In particular, FP loads, stores, and moves now work.
*	[sim,xcc] removed sll32/srl32/sra32 opcodes	Andrew Waterman	2010-08-03
\| \| \| \| \|	These instructions handled static shift amounts >= 32. Since we have a 6-bit shift amount field, these opcodes are no longer necessary.
*	[pk,sim,xcc] Renamed instructions to RISC-V spec	Andrew Waterman	2010-08-03
\| \| \| \| \| \| \|	All word-sized arithmetic operations are now postfixed with 'w', and all double-word-sized arithmetic operations are no longer prefixed with 'd'. mtc0/mfc0 are removed and replaced with mfpcr/mtpcr/mwfpcr/mwtpcr.
*	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	2010-07-28
\| \| \| \| \|	Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes.
*	Reorganized directory structure	Andrew Waterman	2010-07-18
	Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/