riscv-opcodes - RISC-V opcodes

	Commit message (Expand)	Author	Age
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*	[xcc, sim] replaced ble/bleu with bge/bgeu	Andrew Waterman	2010-09-13
*	[opcodes] fixed tex table for ish,ishw types	Yunsup Lee	2010-09-12
*	[opcodes] change rsh to ish types	Yunsup Lee	2010-09-12
*	[opcodes] fixed verilog generation for ish,ishw types	Yunsup Lee	2010-09-12
*	[sim] renamed sllv to sll (same for other shifts)	Andrew Waterman	2010-09-12
*	[xcc, sim] moved shamt field and renamed shifts	Andrew Waterman	2010-09-12
*	[xcc, sim] branches now are next-PC-based, not PC-based	Andrew Waterman	2010-09-12
*	add -verilog option	Yunsup Lee	2010-09-12
*	[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit	Andrew Waterman	2010-09-10
*	[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)	Yunsup Lee	2010-09-10
*	[opcodes] latex table generation added, new opcode mapping	Yunsup Lee	2010-09-10
*	[opcodes,sim,xcc] move opcodes for 3 source instructions	Yunsup Lee	2010-09-09
*	Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"	Andrew Waterman	2010-09-09
*	[xcc, sim] added slei/sleui in lieu of slti/sltiu	Andrew Waterman	2010-09-07
*	[sim, xcc] bthread threading model exposed; insn encoding cleaned up	Andrew Waterman	2010-09-06
*	[sim] added atomic memory operations	Andrew Waterman	2010-09-06
*	[xcc,sim] added fused multiply-add and its cousins	Andrew Waterman	2010-08-22
*	[xcc,sim] Eliminated slori instruction	Andrew Waterman	2010-08-22
*	[xcc,sim] implement FP using softfloat	Andrew Waterman	2010-08-09
*	[sim,xcc] Added first few Hauser FP insns (sign-injection)	Andrew Waterman	2010-08-05
*	[xcc] Removed ctc1, cfc1 instructions; added fp move test case	Andrew Waterman	2010-08-04
*	[xcc,pk,sim] Added first part of FP support	Andrew Waterman	2010-08-04
*	[sim,xcc] removed sll32/srl32/sra32 opcodes	Andrew Waterman	2010-08-03
*	[pk,sim,xcc] Renamed instructions to RISC-V spec	Andrew Waterman	2010-08-03
*	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	2010-07-28
*	Reorganized directory structure	Andrew Waterman	2010-07-18