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author | bunnei <bunneidev@gmail.com> | 2015-05-01 19:05:18 -0400 |
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committer | bunnei <bunneidev@gmail.com> | 2015-05-01 19:05:18 -0400 |
commit | 6a2d8c46f21e8813e0472dba28932ed461ce1a66 (patch) | |
tree | d7057cf9926c822c12cc7d82814a252db79ca600 /src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |
parent | 4d30edc11effef4021a7bd7d5dfe1d92678708b9 (diff) | |
parent | 046dd6e3ef3f4b4da2dd2eef0bdfe0f6fb28b1d8 (diff) |
Merge pull request #713 from bunnei/qt-emuthread-fixes
Fix emulation state resetting to support multiple emulation sessions
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_interpreter.cpp')
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 31 |
1 files changed, 9 insertions, 22 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index fde11e4f..991da740 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -6,7 +6,6 @@ #include <algorithm> #include <cstdio> -#include <unordered_map> #include "common/logging/log.h" #include "common/profiler.h" @@ -3533,25 +3532,6 @@ const transop_fp_t arm_instruction_trans[] = { INTERPRETER_TRANSLATE(blx_1_thumb) }; -typedef std::unordered_map<u32, int> bb_map; -static bb_map CreamCache; - -static void insert_bb(unsigned int addr, int start) { - CreamCache[addr] = start; -} - -static int find_bb(unsigned int addr, int& start) { - int ret = -1; - bb_map::const_iterator it = CreamCache.find(addr); - if (it != CreamCache.end()) { - start = static_cast<int>(it->second); - ret = 0; - } else { - ret = -1; - } - return ret; -} - enum { FETCH_SUCCESS, FETCH_FAILURE @@ -3674,7 +3654,9 @@ translated: } ret = inst_base->br; }; - insert_bb(pc_start, bb_start); + + cpu->instruction_cache[pc_start] = bb_start; + return KEEP_GOING; } @@ -4001,9 +3983,14 @@ unsigned InterpreterMainLoop(ARMul_State* state) { phys_addr = cpu->Reg[15]; - if (find_bb(cpu->Reg[15], ptr) == -1) + // Find the cached instruction cream, otherwise translate it... + auto itr = cpu->instruction_cache.find(cpu->Reg[15]); + if (itr != cpu->instruction_cache.end()) { + ptr = itr->second; + } else { if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) goto END; + } inst_base = (arm_inst *)&inst_buf[ptr]; GOTO_NEXT_INST; |