riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
*	[riscv-isa-run] code cleanup; added README	Andrew Waterman	2011-06-19
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*	[sim, opcodes] made sim more decoupled from opcodes	Andrew Waterman	2011-06-10
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*	[sim,opcodes] improved sim build and run performance	Andrew Waterman	2011-05-29
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*	[pk, sim] added FPU emulation support to proxy kernel	Andrew Waterman	2010-10-15
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*	add -verilog option	Yunsup Lee	2010-09-12
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*	[opcodes] latex table generation added, new opcode mapping	Yunsup Lee	2010-09-10
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*	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	2010-07-28
\| \| \| \| \|	Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes.
*	Reorganized directory structure	Andrew Waterman	2010-07-18
	Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/