riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
*	Go: Return rs2 value for each instructionsHEAD master	Benjamin Barenblat	2016-07-22
\| \| \| \| \|	Some binary floating-point instructions (ab)use the rs2 value to hold additional instruction data, so we need that data in the Go assembler.
*	Go: Make gofmt-clean	Benjamin Barenblat	2016-07-22
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*	Go: Return 'ok' status instead of 'err' status	Benjamin Barenblat	2016-07-22
\| \| \| \|	Also clean up imports.
*	Go: Return errors out of band	Benjamin Barenblat	2016-04-14
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*	Go: Update parse-opcodes to use obj.As	Benjamin Barenblat	2016-03-10
\| \| \| \|	See https://github.com/golang/go/commit/0d9258a830c585.
*	Go: Print CSRs as signed values	Benjamin Barenblat	2016-02-26
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*	Go: Emit all instructions	Benjamin Barenblat	2016-02-22
\| \| \| \| \|	Changes to the RISC-V Go implementation obviate the need for GO_UNUSED_INSTRUCTIONS.
*	Go: Also generate funct3, csr, and funct7 encodings	Benjamin Barenblat	2016-02-22
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*	Clarify use of yank in Go backend	Benjamin Barenblat	2016-01-21
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*	Support generating Go code	Benjamin Barenblat	2016-01-21
\| \| \| \| \|	Generate Go code for the RISC-V Go port <https://github.com/riscv/riscv-go>.
*	add miobase, mipi; drop send_ipi	Andrew Waterman	2015-11-12
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*	In C headers, keep instructions in original input order	Andrew Waterman	2015-09-28
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*	Use BitPat instead of Bits for Chisel3	Andrew Waterman	2015-09-08
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*	update to latest RVC proposal	Andrew Waterman	2015-09-08
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*	Fix DECLARE_CAUSE macros	Andrew Waterman	2015-07-28
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*	New machine-mode timer facility	Andrew Waterman	2015-07-05
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*	Update to privileged architecture version 1.7	Andrew Waterman	2015-05-09
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*	RVC draft	Andrew Waterman	2015-03-30
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*	Merge [shm]call into ecall, [shm]ret into eret	Andrew Waterman	2015-03-17
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*	Update to new privileged spec	Andrew Waterman	2015-03-12
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*	Move stats register	Stephen Twigg	2014-04-03
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*	Add rdcycleh etc. for RV32	Andrew Waterman	2014-03-18
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*	Fix syntax error in generated opcodes	Andrew Waterman	2014-03-11
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*	New FP encoding	Andrew Waterman	2014-03-11
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*	Add fclass.{s\|d} instructions	Andrew Waterman	2014-03-06
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*	Renumber uarch CSRs into custom CSR space	Andrew Waterman	2014-02-14
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*	Reserve 16 uarch-specific read-only userspace counters	Andrew Waterman	2014-02-06
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*	Add DECLARE_CAUSE macro	Andrew Waterman	2014-01-21
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*	Auto-generate exception cause numbers	Andrew Waterman	2014-01-21
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*	New RDCYCLE encoding	Andrew Waterman	2013-12-09
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*	New privileged ISA	Andrew Waterman	2013-11-25
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*	add missing imm for stores	Yunsup Lee	2013-11-22
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*	changes to the instr-table	Yunsup Lee	2013-10-29
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*	revamp hwacha-v3 opcodes	Yunsup Lee	2013-10-10
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*	Fix funct field in tables.	Andrew Waterman	2013-09-21
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*	Update ISA encoding	Andrew Waterman	2013-09-21
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*	hwacha v3: inst format follows the new rocket accelerator extensions	Yunsup Lee	2013-08-07
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*	Rename MTFSR/MFFSR to FSSR/FRSR	Andrew Waterman	2013-08-06
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*	HW ignores upper bits of fence, but SW supplies 0	Andrew Waterman	2013-07-31
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*	tweaks	Yunsup Lee	2013-07-26
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*	Factor out Hwacha/RVC and rename MFTX/MXTF to FMV	Andrew Waterman	2013-07-26
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*	Refactor parse-opcodes	Andrew Waterman	2013-07-25
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*	add auipc, lr, sc	Andrew Waterman	2013-04-17
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*	temporary undoing of renaming	Andrew Waterman	2011-06-19
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*	Renamed packages	Andrew Waterman	2011-06-19
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*	[riscv-isa-run] code cleanup; added README	Andrew Waterman	2011-06-19
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*	[sim, opcodes] made sim more decoupled from opcodes	Andrew Waterman	2011-06-10
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*	[sim,opcodes] improved sim build and run performance	Andrew Waterman	2011-05-29
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*	[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)	Yunsup Lee	2011-05-18
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*	[libs,opcodes,pk,sim,xcc] add mov,fmov, shuffle vec insts	Yunsup Lee	2011-05-15
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