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Author
Age
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changes to the instr-table
Yunsup Lee
2013-10-29
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revamp hwacha-v3 opcodes
Yunsup Lee
2013-10-10
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Fix funct field in tables.
Andrew Waterman
2013-09-21
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Update ISA encoding
Andrew Waterman
2013-09-21
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hwacha v3: inst format follows the new rocket accelerator extensions
Yunsup Lee
2013-08-07
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Rename MTFSR/MFFSR to FSSR/FRSR
Andrew Waterman
2013-08-06
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HW ignores upper bits of fence, but SW supplies 0
Andrew Waterman
2013-07-31
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tweaks
Yunsup Lee
2013-07-26
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Factor out Hwacha/RVC and rename MFTX/MXTF to FMV
Andrew Waterman
2013-07-26
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Refactor parse-opcodes
Andrew Waterman
2013-07-25
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add auipc, lr, sc
Andrew Waterman
2013-04-17
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temporary undoing of renaming
Andrew Waterman
2011-06-19
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Renamed packages
Andrew Waterman
2011-06-19
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[riscv-isa-run] code cleanup; added README
Andrew Waterman
2011-06-19
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[sim, opcodes] made sim more decoupled from opcodes
Andrew Waterman
2011-06-10
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[sim,opcodes] improved sim build and run performance
Andrew Waterman
2011-05-29
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[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)
Yunsup Lee
2011-05-18
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[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts
Yunsup Lee
2011-05-15
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[xcc,sim,opcodes] added c.addiw
Andrew Waterman
2011-04-24
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[xcc,sim,opcodes] added more RVC instructions
Andrew Waterman
2011-04-24
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[xcc,sim] rvc loads and stores
Andrew Waterman
2011-04-12
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[xcc,sim,opcodes] more rvc instructions and bug fixes
Andrew Waterman
2011-04-11
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[xcc, sim] added rvc insn c.li; misc fixes
Andrew Waterman
2011-04-09
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[xcc,pk,sim,opcodes] added first RVC instruction
Andrew Waterman
2011-04-09
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[pk,sim] fixed parse-opcodes bug
Andrew Waterman
2011-04-07
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was causing spurious illegal instruction traps
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[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem ↵
Yunsup Lee
2011-04-05
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instructions
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[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)
Yunsup Lee
2011-04-04
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[opcodes,pk,sim,xcc] add vector mem instructions
Yunsup Lee
2011-04-04
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[opcodes] fixed up instruction table
Andrew Waterman
2011-03-25
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[xcc,pk,opcodes,sim] updated encoding/insn names
Andrew Waterman
2011-03-25
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[opcodes] fixed verilog generation for shifts
Andrew Waterman
2011-01-31
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[opcodes,pk,sim,xcc] great renumbering of 2011, part deux
Andrew Waterman
2011-01-25
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[sim, pk, xcc, opcodes] great instruction renaming of 2011
Andrew Waterman
2011-01-20
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[opcodes,pk,sim,xcc] flip fields to favor little endian
Yunsup Lee
2011-01-03
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[opcodes, pk, sim, xcc] Tweaked FP encoding
Andrew Waterman
2010-11-21
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[opcodes] generate latex and verilog correctly
Andrew Waterman
2010-11-21
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[xcc, sim, pk, opcodes] new instruction encoding!
Andrew Waterman
2010-11-21
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[opcodes, pk, sim, xcc] made jumps shorter and PC-relative
Andrew Waterman
2010-11-21
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[opcodes] add latex table for rm stuff
Yunsup Lee
2010-10-31
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[sim,xcc,pk,opcodes] static rounding modes for FP insns
Andrew Waterman
2010-10-25
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Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
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[opcodes] changed formatting of optab section headers
Andrew Waterman
2010-10-20
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[opcodes] updated parse-opcodes for latex tables
Yunsup Lee
2010-10-05
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[opcodes] update parse-opcodes
Yunsup Lee
2010-10-05
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[xcc, sim] changed instruction format so imm12 subs for rs2
Andrew Waterman
2010-09-20
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[opcodes] fixed tex table for ish,ishw types
Yunsup Lee
2010-09-12
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[opcodes] change rsh to ish types
Yunsup Lee
2010-09-12
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[opcodes] fixed verilog generation for ish,ishw types
Yunsup Lee
2010-09-12
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[xcc, sim] moved shamt field and renamed shifts
Andrew Waterman
2010-09-12
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add -verilog option
Yunsup Lee
2010-09-12
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[opcodes] latex table generation added, new opcode mapping
Yunsup Lee
2010-09-10
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