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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2010-09-12 19:26:33 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2010-09-12 19:44:15 -0700 |
commit | 7ac50f34b0b163efa9fdadc836cffb4b97b24074 (patch) | |
tree | b15d689dfa0b1484eccf1ee472108b8f8a2087f4 /parse-opcodes | |
parent | 4599bddadd22fde723da3ce11e0c0b6772d76398 (diff) |
[opcodes] fixed verilog generation for ish,ishw types
Diffstat (limited to 'parse-opcodes')
-rwxr-xr-x | parse-opcodes | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/parse-opcodes b/parse-opcodes index 4e56615..39f8b89 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -498,25 +498,25 @@ def print_verilog_i_type(name,match,arguments): ) def print_verilog_rsh_type(name,match,arguments): - print "`define %-10s 32'b%s_00000_%s_%s_%s_%s" % \ + print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ + str_verilog_arg('xa','',match,arguments), \ str_verilog_arg('xb','',match,arguments), \ - binary(yank(match,11,4),4), \ - str_verilog_arg('shamt','',match,arguments), \ - str_verilog_arg('xc','',match,arguments) \ + binary(yank(match,5,9),9), \ + str_verilog_arg('shamt','',match,arguments) \ ) def print_verilog_rshw_type(name,match,arguments): - print "`define %-10s 32'b%s_00000_%s_%s_0_%s_%s" % \ + print "`define %-10s 32'b%s_%s_%s_%s_0_%s" % \ ( \ name.replace('.','_').upper(), \ binary(yank(match,25,7),7), \ + str_verilog_arg('xa','',match,arguments), \ str_verilog_arg('xb','',match,arguments), \ - binary(yank(match,11,4),4), \ - str_verilog_arg('shamtw','',match,arguments), \ - str_verilog_arg('xc','',match,arguments) \ + binary(yank(match,5,9),9), \ + str_verilog_arg('shamtw','',match,arguments) \ ) def print_verilog_r4_type(name,match,arguments): |