Commit message (Expand) | Author | Age | |
---|---|---|---|
* | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 2010-09-20 |
* | [opcodes] fixed tex table for ish,ishw types | Yunsup Lee | 2010-09-12 |
* | [opcodes] change rsh to ish types | Yunsup Lee | 2010-09-12 |
* | [opcodes] fixed verilog generation for ish,ishw types | Yunsup Lee | 2010-09-12 |
* | [xcc, sim] moved shamt field and renamed shifts | Andrew Waterman | 2010-09-12 |
* | add -verilog option | Yunsup Lee | 2010-09-12 |
* | [opcodes] latex table generation added, new opcode mapping | Yunsup Lee | 2010-09-10 |
* | [sim] added atomic memory operations | Andrew Waterman | 2010-09-06 |
* | [xcc,sim] added fused multiply-add and its cousins | Andrew Waterman | 2010-08-22 |
* | [sim,xcc] removed sll32/srl32/sra32 opcodes | Andrew Waterman | 2010-08-03 |
* | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 2010-07-28 |
* | Reorganized directory structure | Andrew Waterman | 2010-07-18 |