Commit message (Collapse) | Author | Age | |
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* | [xcc,sim,opcodes] more rvc instructions and bug fixes | 2011-04-11 | |
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* | [xcc, sim] added rvc insn c.li; misc fixes | 2011-04-09 | |
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* | [xcc,pk,sim,opcodes] added first RVC instruction | 2011-04-09 | |
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* | [pk,sim] fixed parse-opcodes bug | 2011-04-07 | |
| | | | | was causing spurious illegal instruction traps | ||
* | [opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem ↵ | 2011-04-05 | |
| | | | | instructions | ||
* | [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.) | 2011-04-04 | |
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* | [opcodes,pk,sim,xcc] add vector mem instructions | 2011-04-04 | |
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* | [opcodes] fixed up instruction table | 2011-03-25 | |
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* | [xcc,pk,opcodes,sim] updated encoding/insn names | 2011-03-25 | |
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* | [opcodes] fixed verilog generation for shifts | 2011-01-31 | |
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* | [opcodes,pk,sim,xcc] great renumbering of 2011, part deux | 2011-01-25 | |
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* | [sim, pk, xcc, opcodes] great instruction renaming of 2011 | 2011-01-20 | |
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* | [opcodes,pk,sim,xcc] flip fields to favor little endian | 2011-01-03 | |
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* | [opcodes, pk, sim, xcc] Tweaked FP encoding | 2010-11-21 | |
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* | [opcodes] generate latex and verilog correctly | 2010-11-21 | |
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* | [xcc, sim, pk, opcodes] new instruction encoding! | 2010-11-21 | |
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* | [opcodes, pk, sim, xcc] made jumps shorter and PC-relative | 2010-11-21 | |
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* | [opcodes] add latex table for rm stuff | 2010-10-31 | |
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* | [sim,xcc,pk,opcodes] static rounding modes for FP insns | 2010-10-25 | |
| | | | | | | Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.) | ||
* | [opcodes] changed formatting of optab section headers | 2010-10-20 | |
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* | [opcodes] updated parse-opcodes for latex tables | 2010-10-05 | |
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* | [opcodes] update parse-opcodes | 2010-10-05 | |
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* | [xcc, sim] changed instruction format so imm12 subs for rs2 | 2010-09-20 | |
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* | [opcodes] fixed tex table for ish,ishw types | 2010-09-12 | |
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* | [opcodes] change rsh to ish types | 2010-09-12 | |
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* | [opcodes] fixed verilog generation for ish,ishw types | 2010-09-12 | |
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* | [xcc, sim] moved shamt field and renamed shifts | 2010-09-12 | |
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* | add -verilog option | 2010-09-12 | |
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* | [opcodes] latex table generation added, new opcode mapping | 2010-09-10 | |
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* | [sim] added atomic memory operations | 2010-09-06 | |
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* | [xcc,sim] added fused multiply-add and its cousins | 2010-08-22 | |
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* | [sim,xcc] removed sll32/srl32/sra32 opcodes | 2010-08-03 | |
| | | | | | These instructions handled static shift amounts >= 32. Since we have a 6-bit shift amount field, these opcodes are no longer necessary. | ||
* | [sim,xcc] Changed instruction format to RISC-V | 2010-07-28 | |
| | | | | | Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes. | ||
* | Reorganized directory structure | 2010-07-18 | |
Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/ |