| Commit message (Collapse) | Author | Age |
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was causing spurious illegal instruction traps
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instructions
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Now, you can either use the RM in the FSR or specify it in the insn.
(Except for FP->int; no dynamic for that.)
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These instructions handled static shift amounts >= 32. Since we have
a 6-bit shift amount field, these opcodes are no longer necessary.
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Massive changes to gcc, binutils to support new instruction encoding.
Simulator reflects these changes.
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Moved cross-compiler to /xcc/ rather than /
Added ISA sim in /sim/
Added Proxy Kernel in /pk/ (to be cleaned up)
Added opcode map to /opcodes/ (ditto)
Added documentation to /doc/
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