riscv-opcodes - RISC-V opcodes

	Commit message (Expand)	Author	Age
*	Rename MTFSR/MFFSR to FSSR/FRSR	Andrew Waterman	2013-08-06
*	HW ignores upper bits of fence, but SW supplies 0	Andrew Waterman	2013-07-31
*	tweaks	Yunsup Lee	2013-07-26
*	Factor out Hwacha/RVC and rename MFTX/MXTF to FMV	Andrew Waterman	2013-07-26
*	Refactor parse-opcodes	Andrew Waterman	2013-07-25
*	add auipc, lr, sc	Andrew Waterman	2013-04-17
*	temporary undoing of renaming	Andrew Waterman	2011-06-19
*	Renamed packages	Andrew Waterman	2011-06-19
*	[riscv-isa-run] code cleanup; added README	Andrew Waterman	2011-06-19
*	[sim, opcodes] made sim more decoupled from opcodes	Andrew Waterman	2011-06-10
*	[sim,opcodes] improved sim build and run performance	Andrew Waterman	2011-05-29
*	[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)	Yunsup Lee	2011-05-18
*	[libs,opcodes,pk,sim,xcc] add mov,fmov, shuffle vec insts	Yunsup Lee	2011-05-15
*	[xcc,sim,opcodes] added c.addiw	Andrew Waterman	2011-04-24
*	[xcc,sim,opcodes] added more RVC instructions	Andrew Waterman	2011-04-24
*	[xcc,sim] rvc loads and stores	Andrew Waterman	2011-04-12
*	[xcc,sim,opcodes] more rvc instructions and bug fixes	Andrew Waterman	2011-04-11
*	[xcc, sim] added rvc insn c.li; misc fixes	Andrew Waterman	2011-04-09
*	[xcc,pk,sim,opcodes] added first RVC instruction	Andrew Waterman	2011-04-09
*	[pk,sim] fixed parse-opcodes bug	Andrew Waterman	2011-04-07
*	[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...	Yunsup Lee	2011-04-05
*	[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)	Yunsup Lee	2011-04-04
*	[opcodes,pk,sim,xcc] add vector mem instructions	Yunsup Lee	2011-04-04
*	[opcodes] fixed up instruction table	Andrew Waterman	2011-03-25
*	[xcc,pk,opcodes,sim] updated encoding/insn names	Andrew Waterman	2011-03-25
*	[opcodes] fixed verilog generation for shifts	Andrew Waterman	2011-01-31
*	[opcodes,pk,sim,xcc] great renumbering of 2011, part deux	Andrew Waterman	2011-01-25
*	[sim, pk, xcc, opcodes] great instruction renaming of 2011	Andrew Waterman	2011-01-20
*	[opcodes,pk,sim,xcc] flip fields to favor little endian	Yunsup Lee	2011-01-03
*	[opcodes, pk, sim, xcc] Tweaked FP encoding	Andrew Waterman	2010-11-21
*	[opcodes] generate latex and verilog correctly	Andrew Waterman	2010-11-21
*	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	2010-11-21
*	[opcodes, pk, sim, xcc] made jumps shorter and PC-relative	Andrew Waterman	2010-11-21
*	[opcodes] add latex table for rm stuff	Yunsup Lee	2010-10-31
*	[sim,xcc,pk,opcodes] static rounding modes for FP insns	Andrew Waterman	2010-10-25
*	[opcodes] changed formatting of optab section headers	Andrew Waterman	2010-10-20
*	[opcodes] updated parse-opcodes for latex tables	Yunsup Lee	2010-10-05
*	[opcodes] update parse-opcodes	Yunsup Lee	2010-10-05
*	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	2010-09-20
*	[opcodes] fixed tex table for ish,ishw types	Yunsup Lee	2010-09-12
*	[opcodes] change rsh to ish types	Yunsup Lee	2010-09-12
*	[opcodes] fixed verilog generation for ish,ishw types	Yunsup Lee	2010-09-12
*	[xcc, sim] moved shamt field and renamed shifts	Andrew Waterman	2010-09-12
*	add -verilog option	Yunsup Lee	2010-09-12
*	[opcodes] latex table generation added, new opcode mapping	Yunsup Lee	2010-09-10
*	[sim] added atomic memory operations	Andrew Waterman	2010-09-06
*	[xcc,sim] added fused multiply-add and its cousins	Andrew Waterman	2010-08-22
*	[sim,xcc] removed sll32/srl32/sra32 opcodes	Andrew Waterman	2010-08-03
*	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	2010-07-28
*	Reorganized directory structure	Andrew Waterman	2010-07-18