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* Rename MTFSR/MFFSR to FSSR/FRSRGravatar Andrew Waterman2013-08-06
* HW ignores upper bits of fence, but SW supplies 0Gravatar Andrew Waterman2013-07-31
* tweaksGravatar Yunsup Lee2013-07-26
* Factor out Hwacha/RVC and rename MFTX/MXTF to FMVGravatar Andrew Waterman2013-07-26
* Refactor parse-opcodesGravatar Andrew Waterman2013-07-25
* add auipc, lr, scGravatar Andrew Waterman2013-04-17
* temporary undoing of renamingGravatar Andrew Waterman2011-06-19
* Renamed packagesGravatar Andrew Waterman2011-06-19
* [riscv-isa-run] code cleanup; added READMEGravatar Andrew Waterman2011-06-19
* [sim, opcodes] made sim more decoupled from opcodesGravatar Andrew Waterman2011-06-10
* [sim,opcodes] improved sim build and run performanceGravatar Andrew Waterman2011-05-29
* [opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Gravatar Yunsup Lee2011-05-18
* [libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsGravatar Yunsup Lee2011-05-15
* [xcc,sim,opcodes] added c.addiwGravatar Andrew Waterman2011-04-24
* [xcc,sim,opcodes] added more RVC instructionsGravatar Andrew Waterman2011-04-24
* [xcc,sim] rvc loads and storesGravatar Andrew Waterman2011-04-12
* [xcc,sim,opcodes] more rvc instructions and bug fixesGravatar Andrew Waterman2011-04-11
* [xcc, sim] added rvc insn c.li; misc fixesGravatar Andrew Waterman2011-04-09
* [xcc,pk,sim,opcodes] added first RVC instructionGravatar Andrew Waterman2011-04-09
* [pk,sim] fixed parse-opcodes bugGravatar Andrew Waterman2011-04-07
* [opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Gravatar Yunsup Lee2011-04-05
* [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Gravatar Yunsup Lee2011-04-04
* [opcodes,pk,sim,xcc] add vector mem instructionsGravatar Yunsup Lee2011-04-04
* [opcodes] fixed up instruction tableGravatar Andrew Waterman2011-03-25
* [xcc,pk,opcodes,sim] updated encoding/insn namesGravatar Andrew Waterman2011-03-25
* [opcodes] fixed verilog generation for shiftsGravatar Andrew Waterman2011-01-31
* [opcodes,pk,sim,xcc] great renumbering of 2011, part deuxGravatar Andrew Waterman2011-01-25
* [sim, pk, xcc, opcodes] great instruction renaming of 2011Gravatar Andrew Waterman2011-01-20
* [opcodes,pk,sim,xcc] flip fields to favor little endianGravatar Yunsup Lee2011-01-03
* [opcodes, pk, sim, xcc] Tweaked FP encodingGravatar Andrew Waterman2010-11-21
* [opcodes] generate latex and verilog correctlyGravatar Andrew Waterman2010-11-21
* [xcc, sim, pk, opcodes] new instruction encoding!Gravatar Andrew Waterman2010-11-21
* [opcodes, pk, sim, xcc] made jumps shorter and PC-relativeGravatar Andrew Waterman2010-11-21
* [opcodes] add latex table for rm stuffGravatar Yunsup Lee2010-10-31
* [sim,xcc,pk,opcodes] static rounding modes for FP insnsGravatar Andrew Waterman2010-10-25
* [opcodes] changed formatting of optab section headersGravatar Andrew Waterman2010-10-20
* [opcodes] updated parse-opcodes for latex tablesGravatar Yunsup Lee2010-10-05
* [opcodes] update parse-opcodesGravatar Yunsup Lee2010-10-05
* [xcc, sim] changed instruction format so imm12 subs for rs2Gravatar Andrew Waterman2010-09-20
* [opcodes] fixed tex table for ish,ishw typesGravatar Yunsup Lee2010-09-12
* [opcodes] change rsh to ish typesGravatar Yunsup Lee2010-09-12
* [opcodes] fixed verilog generation for ish,ishw typesGravatar Yunsup Lee2010-09-12
* [xcc, sim] moved shamt field and renamed shiftsGravatar Andrew Waterman2010-09-12
* add -verilog optionGravatar Yunsup Lee2010-09-12
* [opcodes] latex table generation added, new opcode mappingGravatar Yunsup Lee2010-09-10
* [sim] added atomic memory operationsGravatar Andrew Waterman2010-09-06
* [xcc,sim] added fused multiply-add and its cousinsGravatar Andrew Waterman2010-08-22
* [sim,xcc] removed sll32/srl32/sra32 opcodesGravatar Andrew Waterman2010-08-03
* [sim,xcc] Changed instruction format to RISC-VGravatar Andrew Waterman2010-07-28
* Reorganized directory structureGravatar Andrew Waterman2010-07-18