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RISC-V opcodes
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parse-opcodes
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Author
Age
*
[opcodes] changed formatting of optab section headers
Andrew Waterman
2010-10-20
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[opcodes] updated parse-opcodes for latex tables
Yunsup Lee
2010-10-05
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[opcodes] update parse-opcodes
Yunsup Lee
2010-10-05
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[xcc, sim] changed instruction format so imm12 subs for rs2
Andrew Waterman
2010-09-20
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[opcodes] fixed tex table for ish,ishw types
Yunsup Lee
2010-09-12
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[opcodes] change rsh to ish types
Yunsup Lee
2010-09-12
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[opcodes] fixed verilog generation for ish,ishw types
Yunsup Lee
2010-09-12
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[xcc, sim] moved shamt field and renamed shifts
Andrew Waterman
2010-09-12
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add -verilog option
Yunsup Lee
2010-09-12
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[opcodes] latex table generation added, new opcode mapping
Yunsup Lee
2010-09-10
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[sim] added atomic memory operations
Andrew Waterman
2010-09-06
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[xcc,sim] added fused multiply-add and its cousins
Andrew Waterman
2010-08-22
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[sim,xcc] removed sll32/srl32/sra32 opcodes
Andrew Waterman
2010-08-03
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[sim,xcc] Changed instruction format to RISC-V
Andrew Waterman
2010-07-28
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Reorganized directory structure
Andrew Waterman
2010-07-18