riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
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*	[xcc,sim] implement FP using softfloat	Andrew Waterman	2010-08-09
\| \| \| \|	The intersection of the Hauser FP and MIPS FP is implemented.
*	[sim,xcc] Added first few Hauser FP insns (sign-injection)	Andrew Waterman	2010-08-05
\| \| \| \|	Also updated FPmove test case to test negation and moving between FP regs
*	[xcc] Removed ctc1, cfc1 instructions; added fp move test case	Andrew Waterman	2010-08-04
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*	[xcc,pk,sim] Added first part of FP support	Andrew Waterman	2010-08-04
\| \| \| \|	In particular, FP loads, stores, and moves now work.
*	[sim,xcc] removed sll32/srl32/sra32 opcodes	Andrew Waterman	2010-08-03
\| \| \| \| \|	These instructions handled static shift amounts >= 32. Since we have a 6-bit shift amount field, these opcodes are no longer necessary.
*	[pk,sim,xcc] Renamed instructions to RISC-V spec	Andrew Waterman	2010-08-03
\| \| \| \| \| \| \|	All word-sized arithmetic operations are now postfixed with 'w', and all double-word-sized arithmetic operations are no longer prefixed with 'd'. mtc0/mfc0 are removed and replaced with mfpcr/mtpcr/mwfpcr/mwtpcr.
*	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	2010-07-28
\| \| \| \| \|	Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes.
*	Reorganized directory structure	Andrew Waterman	2010-07-18
	Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/