riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
*	Remove automatically-generated files	Andrew Waterman	2015-09-02
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*	Add rdcycleh etc. for RV32	Andrew Waterman	2014-03-18
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*	New FP encoding	Andrew Waterman	2014-03-11
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*	Add fclass.{s\|d} instructions	Andrew Waterman	2014-03-06
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*	swap JAL/JALR again	Andrew Waterman	2014-01-13
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*	New RDCYCLE encoding	Andrew Waterman	2013-12-09
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*	New privileged ISA	Andrew Waterman	2013-11-25
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*	add missing imm for stores	Yunsup Lee	2013-11-22
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*	fix slli/slliw encoding bug	Yunsup Lee	2013-11-21
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*	changes to the instr-table	Yunsup Lee	2013-10-29
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*	Fix funct field in tables.	Andrew Waterman	2013-09-21
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*	Update ISA encoding	Andrew Waterman	2013-09-21
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*	Rename MTFSR/MFFSR to FSSR/FRSR	Andrew Waterman	2013-08-06
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*	HW ignores upper bits of fence, but SW supplies 0	Andrew Waterman	2013-07-31
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*	Swap J and JALR encodings	Andrew Waterman	2013-07-31
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*	tweaks	Yunsup Lee	2013-07-26
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*	Factor out Hwacha/RVC and rename MFTX/MXTF to FMV	Andrew Waterman	2013-07-26
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*	Refactor parse-opcodes	Andrew Waterman	2013-07-25
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*	add auipc, lr, sc	Andrew Waterman	2013-04-17
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*	change vector fence names/encoding	Andrew Waterman	2012-03-18
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*	opcodes cleanup	Yunsup Lee	2012-03-13
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*	temporary undoing of renaming	Andrew Waterman	2011-06-19
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*	Renamed packages	Andrew Waterman	2011-06-19
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*	[opcodes,pk,sim,xcc] resolve a conflict	Yunsup Lee	2011-05-15
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*	[libs,opcodes,pk,sim,xcc] add mov,fmov, shuffle vec insts	Yunsup Lee	2011-05-15
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*	tweaked encoding of rdcycle & cousins	Andrew Waterman	2011-05-13
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*	[opcodes,pk,sim,xcc] fix utidx - add rd	Yunsup Lee	2011-04-06
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*	[opcodes,pk,sim,xcc] add stop,utidx instructions	Yunsup Lee	2011-04-04
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*	[opcodes,pk,sim,xcc] add fence instructions for vector unit	Yunsup Lee	2011-04-04
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*	[opcodes] fixed up instruction table	Andrew Waterman	2011-03-25
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*	[xcc,pk,opcodes,sim] updated encoding/insn names	Andrew Waterman	2011-03-25
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*	[xcc,opcodes,pk,sim] krste's re-renaming spree	Andrew Waterman	2011-02-15
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*	[xcc,sim,opcodes] removed mtflh/mffl/mffh	Andrew Waterman	2011-02-15
\| \| \| \|	in rv32 these will be replaced with loads and stores.
*	[sim,xcc,opcodes] added back mtflh.d	Andrew Waterman	2011-02-02
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*	[opcodes,pk,sim,xcc] synci now bombs whole icache	Andrew Waterman	2011-02-02
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*	[xcc,opcodes,pk,sim] cleanup to FP ISA	Andrew Waterman	2011-02-01
\| \| \| \| \| \| \|	- Added 5th rounding mode - Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...) - merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode - made MFFL.D and MFFH.D illegal in RV64
*	[sim,opcodes] add mulhsu instruction	Andrew Waterman	2011-01-25
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*	[opcodes,pk,sim,xcc] great renumbering of 2011, part deux	Andrew Waterman	2011-01-25
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*	[sim, pk, xcc, opcodes] great instruction renaming of 2011	Andrew Waterman	2011-01-20
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*	[opcodes, sim, xcc] made *w insns illegal in RV32	Andrew Waterman	2011-01-18
\| \| \| \|	now generic variants behave differently in RV32 and RV64.
*	[opcodes, pk, sim, xcc] removed nor, normalized macros to addi	Andrew Waterman	2011-01-17
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*	[opcodes,pk,sim,xcc] flip fields to favor little endian	Yunsup Lee	2011-01-03
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*	[opcodes, pk, sim, xcc] Tweaked FP encoding	Andrew Waterman	2010-11-21
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*	[opcodes] generate latex and verilog correctly	Andrew Waterman	2010-11-21
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*	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	2010-11-21
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*	[opcodes, pk, sim, xcc] made jumps shorter and PC-relative	Andrew Waterman	2010-11-21
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*	[opcodes] add latex table for rm stuff	Yunsup Lee	2010-10-31
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*	[sim,xcc,pk,opcodes] static rounding modes for FP insns	Andrew Waterman	2010-10-25
\| \| \| \| \| \|	Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
*	[opcodes] changed formatting of optab section headers	Andrew Waterman	2010-10-20
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*	[pk, sim] added FPU emulation support to proxy kernel	Andrew Waterman	2010-10-15
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