Commit message (Expand) | Author | Age | |
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* | [xcc, sim] changed instruction format so imm12 subs for rs2 | 2010-09-20 | |
* | [xcc, sim] replaced ble/bleu with bge/bgeu | 2010-09-13 | |
* | [opcodes] fixed tex table for ish,ishw types | 2010-09-12 | |
* | [opcodes] fixed verilog generation for ish,ishw types | 2010-09-12 | |
* | [sim] renamed sllv to sll (same for other shifts) | 2010-09-12 | |
* | [xcc, sim] moved shamt field and renamed shifts | 2010-09-12 | |
* | [xcc, sim] branches now are next-PC-based, not PC-based | 2010-09-12 | |
* | add -verilog option | 2010-09-12 |