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authorGravatar Yunsup Lee <yunsup@cs.berkeley.edu>2010-09-12 19:26:33 -0700
committerGravatar Yunsup Lee <yunsup@cs.berkeley.edu>2010-09-12 19:44:15 -0700
commit7ac50f34b0b163efa9fdadc836cffb4b97b24074 (patch)
treeb15d689dfa0b1484eccf1ee472108b8f8a2087f4 /inst.v
parent4599bddadd22fde723da3ce11e0c0b6772d76398 (diff)
[opcodes] fixed verilog generation for ish,ishw types
Diffstat (limited to 'inst.v')
-rw-r--r--inst.v12
1 files changed, 6 insertions, 6 deletions
diff --git a/inst.v b/inst.v
index 6451263..f2ce252 100644
--- a/inst.v
+++ b/inst.v
@@ -14,9 +14,9 @@
`define ANDI 32'b1110100_?????_?????_100_????????????
`define ORI 32'b1110100_?????_?????_101_????????????
`define XORI 32'b1110100_?????_?????_110_????????????
-`define SLLI 32'b1110100_00000_?????_1110_??????_00000
-`define SRLI 32'b1110100_00000_?????_1110_??????_00000
-`define SRAI 32'b1110100_00000_?????_1110_??????_00000
+`define SLLI 32'b1110100_?????_?????_110000010_??????
+`define SRLI 32'b1110100_?????_?????_110000100_??????
+`define SRAI 32'b1110100_?????_?????_110000110_??????
`define ADD 32'b1110101_?????_?????_0000000000_?????
`define SUB 32'b1110101_?????_?????_0000000001_?????
`define SLT 32'b1110101_?????_?????_0000000010_?????
@@ -36,9 +36,9 @@
`define REM 32'b1110101_?????_?????_0010000110_?????
`define REMU 32'b1110101_?????_?????_0010000111_?????
`define ADDIW 32'b1110110_?????_?????_000_????????????
-`define SLLIW 32'b1110110_00000_?????_1110_0_?????_00000
-`define SRLIW 32'b1110110_00000_?????_1110_0_?????_00000
-`define SRAIW 32'b1110110_00000_?????_1110_0_?????_00000
+`define SLLIW 32'b1110110_?????_?????_110000010_0_?????
+`define SRLIW 32'b1110110_?????_?????_110000100_0_?????
+`define SRAIW 32'b1110110_?????_?????_110000110_0_?????
`define ADDW 32'b1110111_?????_?????_0000000000_?????
`define SUBW 32'b1110111_?????_?????_0000000001_?????
`define SLLW 32'b1110111_?????_?????_1110000010_?????