riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
*	Merge branch 'confprec'	Quan Nguyen	2014-01-20
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* \|	New privileged ISA	Andrew Waterman	2013-11-25
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\| *	Merge branch 'master' into confprec	Quan Nguyen	2013-11-24
\| \|\ \| \|/ \|/\| \| \| \| \|	Conflicts: Makefile
\| *	Add line in Makefile to parse confprec	Quan Nguyen	2013-11-24
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* \|	fix slli/slliw encoding bug	Yunsup Lee	2013-11-21
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\| *	Move half-precision opcodes to opcodes-hwacha-ut	Quan Nguyen	2013-10-27
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\| *	Add half-precision floating-point instructions	Quan Nguyen	2013-10-17
\|/ \| \| \|	* Add opcodes-hwacha-pseudo to be produced as well, or else GCC will complain.
*	Update ISA encoding	Andrew Waterman	2013-09-21
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*	Add custom opcode space	Andrew Waterman	2013-08-06
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*	Factor out Hwacha/RVC and rename MFTX/MXTF to FMV	Andrew Waterman	2013-07-26
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*	add auipc, lr, sc	Andrew Waterman	2013-04-17
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*	change vector fence names/encoding	Andrew Waterman	2012-03-18
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*	new instructions to handle vector exceptions	Yunsup Lee	2012-03-03
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*	temporary undoing of renaming	Andrew Waterman	2011-06-19
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*	Renamed packages	Andrew Waterman	2011-06-19
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*	[riscv-isa-run] code cleanup; added README	Andrew Waterman	2011-06-19