diff options
| author |  Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-05 00:50:52 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-05 00:50:52 -0700 |
| commit | 2505985a2162b33478fb7da030575cf7beb953f2 (patch) | |
| tree | 688c415de2990b507689377a1ff1efcabdfb5426 /opcodes | |
| parent | 57d01f8e913c0fbd07ec61dae082da0db526d5da (diff) | |
[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem instructions
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes | 156 |
1 files changed, 113 insertions, 43 deletions
@@ -108,6 +108,8 @@ amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3 fence.i rd rs1 imm12 9..7=1 6..2=0x0B 1..0=3 fence rd rs1 imm12 9..7=2 6..2=0x0B 1..0=3 + +# vector fence instructions fence.l.v rd rs1 imm12 9..7=4 6..2=0x0B 1..0=3 fence.g.v rd rs1 imm12 9..7=5 6..2=0x0B 1..0=3 fence.l.cv rd rs1 imm12 9..7=6 6..2=0x0B 1..0=3 @@ -115,6 +117,8 @@ fence.g.cv rd rs1 imm12 9..7=7 6..2=0x0B 1..0=3 syscall 31..27=0 26..22=0 21..17=0 16..7=0 6..2=0x1D 1..0=3 break 31..27=0 26..22=0 21..17=0 16..7=1 6..2=0x1D 1..0=3 + +# vector scalar instructions stop 31..27=0 26..22=0 21..17=0 16..7=2 6..2=0x1D 1..0=3 utidx 31..27=0 26..22=0 21..17=0 16..7=3 6..2=0x1D 1..0=3 @@ -204,46 +208,112 @@ fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 -ld.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lw.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lh.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lb.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 - -sd.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -sw.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -sh.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=1 6..2=0x02 1..0=3 -sb.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=0 6..2=0x02 1..0=3 - -fld.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -flw.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 - -fsd.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -fsw.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -ldst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lwst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lhst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lbst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3 - -sdst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -swst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -shst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=1 6..2=0x02 1..0=3 -sbst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=0 6..2=0x02 1..0=3 - -fldst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -flwst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 - -fsdst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -fswst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -vcfgivl rd rs1 imm12 9..7=0 6..2=0x1C 1..0=3 -setvl rd rs1 21..10=0 9..7=1 6..2=0x1C 1..0=3 -vf 31..27=0 26..22=0 imm12 9..7=2 6..2=0x1C 1..0=3 -mov.vv rd rs1 21..10=0 9..7=3 6..2=0x1C 1..0=3 -fmov.vv rd rs1 21..10=0 9..7=4 6..2=0x1C 1..0=3 +# vector mem instructions + +# 3=d +# 2=seg 2=w +# 1=st 1=st 1=f 1=s 1=h +# 0=u 0=ld 0=x 0=u 0=b +# ---------------------------------------------------------------------------- +# mem padding type ldst x/f u/s width opcode +# unit stride | | | | | | | | +# xloads | | | | | | | | +ld.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +lw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +lwu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +lh.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +lhu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +lb.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +lbu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 +# xstores +sd.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +sw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +sh.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +sb.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +# floads +fld.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +flw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +# fstores +fsd.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +fsw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 + +# mem padding type ldst x/f u/s width opcode +# stride | | | | | | | | +# xloads | | | | | | | | +ldst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +lwst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +lwust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +lhst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +lhust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +lbst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +lbust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 +# xstores +sdst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +swst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +shst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +sbst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +# floads +fldst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +flwst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +# fstores +fsdst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +fswst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 + +# mem padding type ldst x/f u/s width opcode +# segment | | | | | | | | +# xloads | | | | | | | | +ldseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +lwseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +lwuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +lhseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +lhuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +lbseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +lbuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 +# xstores +sdseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +swseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +shseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +sbseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +# floads +fldseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +flwseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +# fstores +fsdseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +fswseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 + +# ldst x/f u/s width opcode +# stride segment | | | | | +# xloads | | | | | +ldsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +lwsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +lwusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=2 6..2=0x03 1..0=3 +lhsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +lhusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=1 6..2=0x03 1..0=3 +lbsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +lbusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=0 6..2=0x03 1..0=3 +# xstores +sdsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +swsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +shsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +sbsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +# floads +fldsegst.v rd rs1 rs2 rs3 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +flwsegst.v rd rs1 rs2 rs3 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 +# fstores +fsdsegst.v rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +fswsegst.v rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# vector arithmetic instructions +mov.vv rd rs1 21..17=0 16=1 15=0 14..12=0 11..7=0 6..2=0x02 1..0=3 +mov.sv rd rs1 21..17=0 16=1 15=0 14..12=0 11..7=1 6..2=0x02 1..0=3 +mov.su rd rs1 rs2 16=1 15=0 14..12=0 11..7=2 6..2=0x02 1..0=3 +mov.us rd rs1 rs2 16=1 15=0 14..12=0 11..7=3 6..2=0x02 1..0=3 +fmov.vv rd rs1 21..17=0 16=1 15=1 14..12=0 11..7=0 6..2=0x02 1..0=3 +fmov.sv rd rs1 21..17=0 16=1 15=1 14..12=0 11..7=1 6..2=0x02 1..0=3 +fmov.su rd rs1 rs2 16=1 15=1 14..12=0 11..7=2 6..2=0x02 1..0=3 +fmov.us rd rs1 rs2 16=1 15=1 14..12=0 11..7=3 6..2=0x02 1..0=3 + +# vector immediate instructions +vcfgivl rd rs1 imm12 9..7=0 6..2=0x1C 1..0=3 +setvl rd rs1 21..10=0 9..7=1 6..2=0x1C 1..0=3 +vf 31..27=0 rs1 imm12 9..7=2 6..2=0x1C 1..0=3 |