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authorGravatar Quan Nguyen <quannguyen@berkeley.edu>2013-11-24 22:04:23 -0800
committerGravatar Quan Nguyen <quannguyen@berkeley.edu>2013-11-24 22:04:23 -0800
commitd75c0f77fb66b0013f62080fc96acce680e4cc8f (patch)
tree024a4861f1a7befbbfda80fcf2678a9ce3f3f66d /inst.chisel
parent128c2b7ef1790b39dc43b5aa2b0876becff01440 (diff)
parentbc445390566f8831dd8bb34bcc05d80c7401296a (diff)
Merge branch 'master' into confprec
Conflicts: Makefile
Diffstat (limited to 'inst.chisel')
-rw-r--r--inst.chisel4
1 files changed, 2 insertions, 2 deletions
diff --git a/inst.chisel b/inst.chisel
index b77863a..abda1c6 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -10,7 +10,7 @@
def LUI = Bits("b?????????????????????????0110111")
def AUIPC = Bits("b?????????????????????????0010111")
def ADDI = Bits("b?????????????????000?????0010011")
- def SLLI = Bits("b010000???????????001?????0010011")
+ def SLLI = Bits("b000000???????????001?????0010011")
def SLTI = Bits("b?????????????????010?????0010011")
def SLTIU = Bits("b?????????????????011?????0010011")
def XORI = Bits("b?????????????????100?????0010011")
@@ -37,7 +37,7 @@
def REM = Bits("b0000001??????????110?????0110011")
def REMU = Bits("b0000001??????????111?????0110011")
def ADDIW = Bits("b?????????????????000?????0011011")
- def SLLIW = Bits("b0100000??????????001?????0011011")
+ def SLLIW = Bits("b0000000??????????001?????0011011")
def SRLIW = Bits("b0000000??????????101?????0011011")
def SRAIW = Bits("b0100000??????????101?????0011011")
def ADDW = Bits("b0000000??????????000?????0111011")