Update to privileged architecture version 1.7

6 files changed, 243 insertions, 124 deletions

diff --git a/Makefile b/Makefile
index 54e9999..3cacc0a 100644
--- a/Makefile
+++ b/Makefile
@@ -10,7 +10,7 @@ XCC_H := ../riscv-gnu-toolchain/gcc/gcc/config/riscv/riscv-opc.h
 
 ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom
 
-install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex
+install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex priv-instr-table.tex
 
 $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes encoding.h
 	cp encoding.h $@
@@ -30,4 +30,7 @@ inst.chisel: $(ALL_OPCODES) parse-opcodes
 instr-table.tex: $(ALL_OPCODES) parse-opcodes
 	cat opcodes opcodes-pseudo | ./parse-opcodes -tex > $@
 
+priv-instr-table.tex: $(ALL_OPCODES) parse-opcodes
+	cat opcodes opcodes-pseudo | ./parse-opcodes -privtex > $@
+
 .PHONY : install
diff --git a/encoding.h b/encoding.h
index b731f50..b404e8d 100644
--- a/encoding.h
+++ b/encoding.h
@@ -3,42 +3,41 @@
 #ifndef RISCV_CSR_ENCODING_H
 #define RISCV_CSR_ENCODING_H
 
-#define MSTATUS_SSIP        0x00000002
-#define MSTATUS_HSIP        0x00000004
-#define MSTATUS_MSIP        0x00000008
-#define MSTATUS_IE          0x00000010
-#define MSTATUS_PRV         0x00000060
-#define MSTATUS_IE1         0x00000080
-#define MSTATUS_PRV1        0x00000300
-#define MSTATUS_IE2         0x00000400
-#define MSTATUS_PRV2        0x00001800
-#define MSTATUS_IE3         0x00002000
-#define MSTATUS_PRV3        0x0000C000
-#define MSTATUS_MPRV        0x00030000
-#define MSTATUS_VM          0x00780000
-#define MSTATUS_STIE        0x01000000
-#define MSTATUS_HTIE        0x02000000
-#define MSTATUS_MTIE        0x04000000
-#define MSTATUS_FS          0x18000000
-#define MSTATUS_XS          0x60000000
+#define MSTATUS_IE          0x00000001
+#define MSTATUS_PRV         0x00000006
+#define MSTATUS_IE1         0x00000008
+#define MSTATUS_PRV1        0x00000030
+#define MSTATUS_IE2         0x00000040
+#define MSTATUS_PRV2        0x00000180
+#define MSTATUS_IE3         0x00000200
+#define MSTATUS_PRV3        0x00000C00
+#define MSTATUS_FS          0x00003000
+#define MSTATUS_XS          0x0000C000
+#define MSTATUS_MPRV        0x00010000
+#define MSTATUS_VM          0x003E0000
 #define MSTATUS32_SD        0x80000000
-#define MSTATUS64_UA        0x0000000F00000000
-#define MSTATUS64_SA        0x000000F000000000
-#define MSTATUS64_HA        0x00000F0000000000
 #define MSTATUS64_SD        0x8000000000000000
 
-#define SSTATUS_SIP         0x00000002
-#define SSTATUS_IE          0x00000010
-#define SSTATUS_PIE         0x00000080
-#define SSTATUS_PS          0x00000100
-#define SSTATUS_UA          0x000F0000
+#define SSTATUS_IE          0x00000001
+#define SSTATUS_PIE         0x00000008
+#define SSTATUS_PS          0x00000010
+#define SSTATUS_FS          0x00003000
+#define SSTATUS_XS          0x0000C000
+#define SSTATUS_MPRV        0x00010000
 #define SSTATUS_TIE         0x01000000
-#define SSTATUS_TIP         0x04000000
-#define SSTATUS_FS          0x18000000
-#define SSTATUS_XS          0x60000000
 #define SSTATUS32_SD        0x80000000
 #define SSTATUS64_SD        0x8000000000000000
 
+#define MIP_SSIP            0x00000002
+#define MIP_HSIP            0x00000004
+#define MIP_MSIP            0x00000008
+#define MIP_STIP            0x00000200
+#define MIP_HTIP            0x00000400
+#define MIP_MTIP            0x00000800
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
 #define PRV_U 0
 #define PRV_S 1
 #define PRV_H 2
@@ -55,65 +54,64 @@
 #define UA_RV64  4
 #define UA_RV128 8
 
-#define IRQ_TIMER  0
-#define IRQ_IPI    1
+#define IRQ_SOFT   0
+#define IRQ_TIMER  1
 #define IRQ_HOST   2
 #define IRQ_COP    3
 
-#define IMPL_SPIKE  1
-#define IMPL_ROCKET 2
+#define IMPL_ROCKET 1
+
+#define DEFAULT_MTVEC 0x100
 
 // page table entry (PTE) fields
-#define PTE_TYPE   0x007
-#define PTE_PERM   0x018
-#define PTE_G      0x020 // Global
-#define PTE_R      0x040 // Referenced
-#define PTE_D      0x080 // Dirty
-#define PTE_SOFT   0x300 // Reserved for Software
-#define RV64_PTE_PPN_SHIFT 26
-#define RV32_PTE_PPN_SHIFT 10
-#define PTE_TYPE_INVALID 0
-#define PTE_TYPE_TABLE   1
-#define PTE_TYPE_U       2
-#define PTE_TYPE_S       3
-#define PTE_TYPE_US      4
-#define PTE_TYPE_US_SR   4
-#define PTE_TYPE_US_SRW  5
-#define PTE_TYPE_US_SRX  6
-#define PTE_TYPE_US_SRWX 7
-
-#define PROT_TO_PERM(PROT) ((((PROT) & PROT_EXEC) ? 2 : 0) | (((PROT) & PROT_WRITE) ? 1 : 0))
-#define PTE_CREATE(PPN, PERM_U, PERM_S) \
-  (((PPN) << PTE_PPN_SHIFT) | (PROT_TO_PERM(PERM_U) << 3) | \
-   ((PERM_U) && (PERM_S) ? (PTE_TYPE_US | PROT_TO_PERM(PERM_S)) : \
-   (PERM_S) ? (PTE_TYPE_S | (PROT_TO_PERM(PERM_S) << 3)) : \
-   (PERM_U) ? PTE_TYPE_U : 0))
-
-#define PTE_UR(PTE) ((0xF4F4F4F4U >> ((PTE) & 0x1f)) & 1)
-#define PTE_UW(PTE) ((0xF400F400U >> ((PTE) & 0x1f)) & 1)
-#define PTE_UX(PTE) ((0xF4F40000U >> ((PTE) & 0x1f)) & 1)
-#define PTE_SR(PTE) ((0xF8F8F8F8U >> ((PTE) & 0x1f)) & 1)
-#define PTE_SW(PTE) ((0xA8A0A8A0U >> ((PTE) & 0x1f)) & 1)
-#define PTE_SX(PTE) ((0xC8C8C0C0U >> ((PTE) & 0x1f)) & 1)
-#define PTE_CHECK_PERM(PTE, SUPERVISOR, WRITE, EXEC) \
-  ((SUPERVISOR) ? ((WRITE) ? PTE_SW(PTE) : (EXEC) ? PTE_SX(PTE) : PTE_SR(PTE)) \
-                : ((WRITE) ? PTE_UW(PTE) : (EXEC) ? PTE_UX(PTE) : PTE_UR(PTE)))
+#define PTE_V     0x001 // Valid
+#define PTE_TYPE  0x01E // Type
+#define PTE_R     0x020 // Referenced
+#define PTE_D     0x040 // Dirty
+#define PTE_SOFT  0x380 // Reserved for Software
+
+#define PTE_TYPE_TABLE        0x00
+#define PTE_TYPE_TABLE_GLOBAL 0x02
+#define PTE_TYPE_URX_SR       0x04
+#define PTE_TYPE_URWX_SRW     0x06
+#define PTE_TYPE_UR_SR        0x08
+#define PTE_TYPE_URW_SRW      0x0A
+#define PTE_TYPE_URX_SRX      0x0C
+#define PTE_TYPE_URWX_SRWX    0x0E
+#define PTE_TYPE_SR           0x10
+#define PTE_TYPE_SRW          0x12
+#define PTE_TYPE_SRX          0x14
+#define PTE_TYPE_SRWX         0x16
+#define PTE_TYPE_SR_GLOBAL    0x18
+#define PTE_TYPE_SRW_GLOBAL   0x1A
+#define PTE_TYPE_SRX_GLOBAL   0x1C
+#define PTE_TYPE_SRWX_GLOBAL  0x1E
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
+#define PTE_UR(PTE)    ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UW(PTE)    ((0x00008880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UX(PTE)    ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SR(PTE)    ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SW(PTE)    ((0x88888880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SX(PTE)    ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
+
+#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
+  ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
+   (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
+             ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
 
 #ifdef __riscv
 
 #ifdef __riscv64
-# define MSTATUS_UA MSTATUS64_UA
-# define MSTATUS_SA MSTATUS64_SA
-# define MSTATUS_HA MSTATUS64_HA
 # define MSTATUS_SD MSTATUS64_SD
 # define SSTATUS_SD SSTATUS64_SD
 # define RISCV_PGLEVEL_BITS 9
-# define PTE_PPN_SHIFT RV64_PTE_PPN_SHIFT
 #else
 # define MSTATUS_SD MSTATUS32_SD
 # define SSTATUS_SD SSTATUS32_SD
 # define RISCV_PGLEVEL_BITS 10
-# define PTE_PPN_SHIFT RV32_PTE_PPN_SHIFT
 #endif
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
diff --git a/inst.chisel b/inst.chisel
index 20362d3..0c49d6c 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -90,7 +90,10 @@ object Instructions {
   def SBREAK             = Bits("b00000000000100000000000001110011")
   def SRET               = Bits("b00010000000000000000000001110011")
   def SFENCE_VM          = Bits("b000100000001?????000000001110011")
+  def WFI                = Bits("b00010000001000000000000001110011")
+  def MRTH               = Bits("b00110000011000000000000001110011")
   def MRTS               = Bits("b00110000010100000000000001110011")
+  def HRTS               = Bits("b00100000010100000000000001110011")
   def CSRRW              = Bits("b?????????????????001?????1110011")
   def CSRRS              = Bits("b?????????????????010?????1110011")
   def CSRRC              = Bits("b?????????????????011?????1110011")
@@ -188,23 +191,29 @@ object Causes {
   val misaligned_fetch = 0x0
   val fault_fetch = 0x1
   val illegal_instruction = 0x2
+  val breakpoint = 0x3
   val misaligned_load = 0x4
   val fault_load = 0x5
   val misaligned_store = 0x6
   val fault_store = 0x7
-  val ecall = 0x8
-  val breakpoint = 0x9
+  val user_ecall = 0x8
+  val supervisor_ecall = 0x9
+  val hypervisor_ecall = 0xa
+  val machine_ecall = 0xb
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
     res += misaligned_fetch
     res += fault_fetch
     res += illegal_instruction
+    res += breakpoint
     res += misaligned_load
     res += fault_load
     res += misaligned_store
     res += fault_store
-    res += ecall
-    res += breakpoint
+    res += user_ecall
+    res += supervisor_ecall
+    res += hypervisor_ecall
+    res += machine_ecall
     res.toArray
   }
 }
@@ -234,32 +243,47 @@ object CSRs {
   val uarch15 = 0xccf
   val sstatus = 0x100
   val stvec = 0x101
+  val sie = 0x104
   val stimecmp = 0x121
   val sscratch = 0x140
   val sepc = 0x141
-  val sptbr = 0x188
-  val sasid = 0x189
-  val scycle = 0x900
-  val stime = 0x901
-  val sinstret = 0x902
-  val scause = 0xd40
-  val sbadaddr = 0xd41
+  val sip = 0x144
+  val sptbr = 0x180
+  val sasid = 0x181
+  val cyclew = 0x900
+  val timew = 0x901
+  val instretw = 0x902
+  val stime = 0xd01
+  val scause = 0xd42
+  val sbadaddr = 0xd43
+  val stimew = 0xa01
   val mstatus = 0x300
+  val mtvec = 0x301
+  val mtdeleg = 0x302
+  val mie = 0x304
+  val mtimecmp = 0x321
   val mscratch = 0x340
   val mepc = 0x341
   val mcause = 0x342
   val mbadaddr = 0x343
-  val reset = 0x780
-  val tohost = 0x781
-  val fromhost = 0x782
+  val mip = 0x344
+  val mtime = 0x701
+  val mcpuid = 0xf00
+  val mimpid = 0xf01
+  val mhartid = 0xf10
+  val mtohost = 0x780
+  val mfromhost = 0x781
+  val mreset = 0x782
   val send_ipi = 0x783
-  val hartid = 0xfc0
   val cycleh = 0xc80
   val timeh = 0xc81
   val instreth = 0xc82
-  val scycleh = 0x980
-  val stimeh = 0x981
-  val sinstreth = 0x982
+  val cyclehw = 0x980
+  val timehw = 0x981
+  val instrethw = 0x982
+  val stimeh = 0xd81
+  val stimehw = 0xa81
+  val mtimeh = 0x741
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
     res += fflags
@@ -287,26 +311,38 @@ object CSRs {
     res += uarch15
     res += sstatus
     res += stvec
+    res += sie
     res += stimecmp
     res += sscratch
     res += sepc
+    res += sip
     res += sptbr
     res += sasid
-    res += scycle
+    res += cyclew
+    res += timew
+    res += instretw
     res += stime
-    res += sinstret
     res += scause
     res += sbadaddr
+    res += stimew
     res += mstatus
+    res += mtvec
+    res += mtdeleg
+    res += mie
+    res += mtimecmp
     res += mscratch
     res += mepc
     res += mcause
     res += mbadaddr
-    res += reset
-    res += tohost
-    res += fromhost
+    res += mip
+    res += mtime
+    res += mcpuid
+    res += mimpid
+    res += mhartid
+    res += mtohost
+    res += mfromhost
+    res += mreset
     res += send_ipi
-    res += hartid
     res.toArray
   }
   val all32 = {
@@ -314,9 +350,12 @@ object CSRs {
     res += cycleh
     res += timeh
     res += instreth
-    res += scycleh
+    res += cyclehw
+    res += timehw
+    res += instrethw
     res += stimeh
-    res += sinstreth
+    res += stimehw
+    res += mtimeh
     res.toArray
   }
 }
diff --git a/opcodes b/opcodes
index 4ef1397..1f15231 100644
--- a/opcodes
+++ b/opcodes
@@ -117,7 +117,10 @@ scall     11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3
 sbreak    11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3
 sret      11..7=0 19..15=0 31..20=0x100 14..12=0 6..2=0x1C 1..0=3
 sfence.vm 11..7=0 rs1      31..20=0x101 14..12=0 6..2=0x1C 1..0=3
+wfi       11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3
+mrth      11..7=0 19..15=0 31..20=0x306 14..12=0 6..2=0x1C 1..0=3
 mrts      11..7=0 19..15=0 31..20=0x305 14..12=0 6..2=0x1C 1..0=3
+hrts      11..7=0 19..15=0 31..20=0x205 14..12=0 6..2=0x1C 1..0=3
 csrrw     rd      rs1      imm12        14..12=1 6..2=0x1C 1..0=3
 csrrs     rd      rs1      imm12        14..12=2 6..2=0x1C 1..0=3
 csrrc     rd      rs1      imm12        14..12=3 6..2=0x1C 1..0=3
diff --git a/opcodes-pseudo b/opcodes-pseudo
index 4171e7e..20c83ec 100644
--- a/opcodes-pseudo
+++ b/opcodes-pseudo
@@ -18,3 +18,8 @@
 @rdcycleh   rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3
 @rdtimeh    rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3
 @rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3
+
+# Krste can't decide how to name these instructions
+@ecall     11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3
+@ebreak    11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3
+@eret      11..7=0 19..15=0 31..20=0x100 14..12=0 6..2=0x1C 1..0=3
diff --git a/parse-opcodes b/parse-opcodes
index 174602b..d3987dd 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -34,12 +34,15 @@ causes = [
   (0x00, 'misaligned fetch'),
   (0x01, 'fault fetch'),
   (0x02, 'illegal instruction'),
+  (0x03, 'breakpoint'),
   (0x04, 'misaligned load'),
   (0x05, 'fault load'),
   (0x06, 'misaligned store'),
   (0x07, 'fault store'),
-  (0x08, 'ecall'),
-  (0x09, 'breakpoint'),
+  (0x08, 'user_ecall'),
+  (0x09, 'supervisor_ecall'),
+  (0x0A, 'hypervisor_ecall'),
+  (0x0B, 'machine_ecall'),
 ]
 
 csrs = [
@@ -77,36 +80,50 @@ csrs = [
   # Standard Supervisor R/W
   (0x100, 'sstatus'),
   (0x101, 'stvec'),
+  (0x104, 'sie'),
   (0x121, 'stimecmp'),
   (0x140, 'sscratch'),
   (0x141, 'sepc'),
-  (0x188, 'sptbr'),
-  (0x189, 'sasid'),
+  (0x144, 'sip'),
+  (0x180, 'sptbr'),
+  (0x181, 'sasid'),
 
   # Standard Supervisor R/W Shadows of User RO
-  (0x900, 'scycle'),
-  (0x901, 'stime'),
-  (0x902, 'sinstret'),
+  (0x900, 'cyclew'),
+  (0x901, 'timew'),
+  (0x902, 'instretw'),
 
   # Standard Supervisor RO
-  (0xD40, 'scause'),
-  (0xD41, 'sbadaddr'),
+  (0xD01, 'stime'),
+  (0xD42, 'scause'),
+  (0xD43, 'sbadaddr'),
+
+  # Standard Hypervisor R/W Shadows of Supervisor RO
+  (0xA01, 'stimew'),
 
   # Standard Machine R/W
   (0x300, 'mstatus'),
+  (0x301, 'mtvec'),
+  (0x302, 'mtdeleg'),
+  (0x304, 'mie'),
+  (0x321, 'mtimecmp'),
   (0x340, 'mscratch'),
   (0x341, 'mepc'),
   (0x342, 'mcause'),
   (0x343, 'mbadaddr'),
+  (0x344, 'mip'),
+  (0x701, 'mtime'),
+
+  # Standard Machine RO
+  (0xF00, 'mcpuid'),
+  (0xF01, 'mimpid'),
+  (0xF10, 'mhartid'),
 
   # Nonstandard Machine R/W
-  (0x780, 'reset'),
-  (0x781, 'tohost'),
-  (0x782, 'fromhost'),
+  (0x780, 'mtohost'),
+  (0x781, 'mfromhost'),
+  (0x782, 'mreset'),
   (0x783, 'send_ipi'),
-
-  # Nonstandard Machine RO
-  (0xFC0, 'hartid'),
 ]
 
 csrs32 = [
@@ -116,9 +133,18 @@ csrs32 = [
   (0xC82, 'instreth'),
 
   # Standard Supervisor R/W Shadows of User RO
-  (0x980, 'scycleh'),
-  (0x981, 'stimeh'),
-  (0x982, 'sinstreth'),
+  (0x980, 'cyclehw'),
+  (0x981, 'timehw'),
+  (0x982, 'instrethw'),
+
+  # Standard Supervisor RO
+  (0xD81, 'stimeh'),
+
+  # Standard Hypervisor R/W Shadows of Supervisor RO
+  (0xA81, 'stimehw'),
+
+  # Standard Machine R/W
+  (0x741, 'mtimeh'),
 ]
 
 opcode_base = 0
@@ -181,6 +207,11 @@ def str_inst(name,arguments):
     arguments.remove('bimm12hi')
     arguments.remove('bimm12lo')
     arguments.append('imm')
+  if name[:3] == 'csr':
+    arguments.remove('imm12')
+    arguments.remove('rs1')
+    arguments.append('csr')
+    arguments.append('imm' if name[-1] == 'i' else 'rs1')
   if 'imm12' in arguments:
     arguments.remove('imm12')
     arguments.append('imm')
@@ -312,6 +343,25 @@ def print_i_type(name,match,arguments):
     str_inst(name,arguments) \
   )
 
+def print_csr_type(name,match,arguments):
+  print """
+&
+\\multicolumn{6}{|c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} &
+\\multicolumn{1}{c|}{%s} & %s \\\\
+\\cline{2-11}
+  """ % \
+  ( \
+    str_arg('imm12','csr',match,arguments), \
+    ('zimm' if name[-1] == 'i' else 'rs1'), \
+    binary(yank(match,funct_base,funct_size),funct_size), \
+    str_arg('rd','',match,arguments), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
 def print_ish_type(name,match,arguments):
   print """
 &
@@ -547,7 +597,7 @@ def print_subtitle(title):
 \\cline{2-11}
   """ % title
 
-def print_footer(caption):
+def print_footer(caption=''):
   print """
 \\end{tabular}
 \\end{center}
@@ -555,9 +605,11 @@ def print_footer(caption):
 %s
 \\label{instr-table}
 \\end{table}
-  """ % (caption and '\\caption{Instruction listing for RISC-V}' or '')
+  """ % caption
 
 def print_inst(n):
+  is_system = (match[n] & 0x7f) == (match['scall'] & 0x7f)
+
   if n == 'fence' or n == 'fence.i':
     print_fence_type(n, match[n], arguments[n])
   elif 'aqrl' in arguments[n]:
@@ -570,7 +622,9 @@ def print_inst(n):
     print_u_type(n, match[n], arguments[n])
   elif 'jimm20' in arguments[n]:
     print_uj_type(n, match[n], arguments[n])
-  elif 'imm12' in arguments[n] or (match[n] & 0x7f) == (match['scall'] & 0x7f):
+  elif is_system and n[:3] == 'csr':
+    print_csr_type(n, match[n], arguments[n])
+  elif 'imm12' in arguments[n] or is_system:
     print_i_type(n, match[n], arguments[n])
   elif 'imm12hi' in arguments[n]:
     print_s_type(n, match[n], arguments[n])
@@ -585,6 +639,21 @@ def print_insts(*names):
   for n in names:
     print_inst(n)
 
+def make_supervisor_latex_table():
+  print_header('i')
+  print_subtitle('Instructions to Access CSRs')
+  print_insts('csrrw', 'csrrs', 'csrrc')
+  print_insts('csrrwi', 'csrrsi', 'csrrci')
+  print_subtitle('Instructions to Change Privilege Level')
+  print_insts('ecall', 'ebreak', 'eret')
+  print_subtitle('Trap-Redirection Instructions')
+  print_insts('mrts', 'mrth', 'hrts')
+  print_subtitle('Interrupt-Management Instructions')
+  print_insts('wfi')
+  print_subtitle('Memory-Management Instructions')
+  print_insts('sfence.vm')
+  print_footer('\\caption{RISC-V Privileged Instructions}')
+
 def make_latex_table():
   print_header('r','i','s','sb','u','uj')
   print_subtitle('RV32I Base Instruction Set')
@@ -598,7 +667,7 @@ def make_latex_table():
   print_insts('rdcycle', 'rdcycleh')
   print_insts('rdtime', 'rdtimeh')
   print_insts('rdinstret', 'rdinstreth')
-  print_footer(0)
+  print_footer()
 
   print_header('r','a','i','s')
   print_subtitle('RV64I Base Instruction Set (in addition to RV32I)')
@@ -616,7 +685,7 @@ def make_latex_table():
   print_insts('amoswap.w')
   print_insts('amoadd.w', 'amoxor.w', 'amoand.w', 'amoor.w')
   print_insts('amomin.w', 'amomax.w', 'amominu.w', 'amomaxu.w')
-  print_footer(0)
+  print_footer()
 
   print_header('r','r4','i','s')
   print_subtitle('RV64A Standard Extension (in addition to RV32A)')
@@ -634,7 +703,7 @@ def make_latex_table():
   print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.s.x')
   print_insts('frcsr', 'frrm', 'frflags')
   print_insts('fscsr', 'fsrm', 'fsflags', 'fsrmi', 'fsflagsi')
-  print_footer(0)
+  print_footer()
 
   print_header('r','r4','i','s')
   print_subtitle('RV64F Standard Extension (in addition to RV32F)')
@@ -652,7 +721,7 @@ def make_latex_table():
   print_subtitle('RV64D Standard Extension (in addition to RV32D)')
   print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d')
   print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x')
-  print_footer(1)
+  print_footer('\\caption{Instruction listing for RISC-V}')
 
 def print_chisel_insn(name):
   s = "  def %-18s = Bits(\"b" % name.replace('.', '_').upper()
@@ -761,6 +830,8 @@ for line in sys.stdin:
 
 if sys.argv[1] == '-tex':
   make_latex_table()
+elif sys.argv[1] == '-privtex':
+  make_supervisor_latex_table()
 elif sys.argv[1] == '-chisel':
   make_chisel()
 elif sys.argv[1] == '-c':