1 files changed, 65 insertions, 26 deletions

diff --git a/inst.chisel b/inst.chisel
index 20362d3..0c49d6c 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -90,7 +90,10 @@ object Instructions {
   def SBREAK             = Bits("b00000000000100000000000001110011")
   def SRET               = Bits("b00010000000000000000000001110011")
   def SFENCE_VM          = Bits("b000100000001?????000000001110011")
+  def WFI                = Bits("b00010000001000000000000001110011")
+  def MRTH               = Bits("b00110000011000000000000001110011")
   def MRTS               = Bits("b00110000010100000000000001110011")
+  def HRTS               = Bits("b00100000010100000000000001110011")
   def CSRRW              = Bits("b?????????????????001?????1110011")
   def CSRRS              = Bits("b?????????????????010?????1110011")
   def CSRRC              = Bits("b?????????????????011?????1110011")
@@ -188,23 +191,29 @@ object Causes {
   val misaligned_fetch = 0x0
   val fault_fetch = 0x1
   val illegal_instruction = 0x2
+  val breakpoint = 0x3
   val misaligned_load = 0x4
   val fault_load = 0x5
   val misaligned_store = 0x6
   val fault_store = 0x7
-  val ecall = 0x8
-  val breakpoint = 0x9
+  val user_ecall = 0x8
+  val supervisor_ecall = 0x9
+  val hypervisor_ecall = 0xa
+  val machine_ecall = 0xb
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
     res += misaligned_fetch
     res += fault_fetch
     res += illegal_instruction
+    res += breakpoint
     res += misaligned_load
     res += fault_load
     res += misaligned_store
     res += fault_store
-    res += ecall
-    res += breakpoint
+    res += user_ecall
+    res += supervisor_ecall
+    res += hypervisor_ecall
+    res += machine_ecall
     res.toArray
   }
 }
@@ -234,32 +243,47 @@ object CSRs {
   val uarch15 = 0xccf
   val sstatus = 0x100
   val stvec = 0x101
+  val sie = 0x104
   val stimecmp = 0x121
   val sscratch = 0x140
   val sepc = 0x141
-  val sptbr = 0x188
-  val sasid = 0x189
-  val scycle = 0x900
-  val stime = 0x901
-  val sinstret = 0x902
-  val scause = 0xd40
-  val sbadaddr = 0xd41
+  val sip = 0x144
+  val sptbr = 0x180
+  val sasid = 0x181
+  val cyclew = 0x900
+  val timew = 0x901
+  val instretw = 0x902
+  val stime = 0xd01
+  val scause = 0xd42
+  val sbadaddr = 0xd43
+  val stimew = 0xa01
   val mstatus = 0x300
+  val mtvec = 0x301
+  val mtdeleg = 0x302
+  val mie = 0x304
+  val mtimecmp = 0x321
   val mscratch = 0x340
   val mepc = 0x341
   val mcause = 0x342
   val mbadaddr = 0x343
-  val reset = 0x780
-  val tohost = 0x781
-  val fromhost = 0x782
+  val mip = 0x344
+  val mtime = 0x701
+  val mcpuid = 0xf00
+  val mimpid = 0xf01
+  val mhartid = 0xf10
+  val mtohost = 0x780
+  val mfromhost = 0x781
+  val mreset = 0x782
   val send_ipi = 0x783
-  val hartid = 0xfc0
   val cycleh = 0xc80
   val timeh = 0xc81
   val instreth = 0xc82
-  val scycleh = 0x980
-  val stimeh = 0x981
-  val sinstreth = 0x982
+  val cyclehw = 0x980
+  val timehw = 0x981
+  val instrethw = 0x982
+  val stimeh = 0xd81
+  val stimehw = 0xa81
+  val mtimeh = 0x741
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
     res += fflags
@@ -287,26 +311,38 @@ object CSRs {
     res += uarch15
     res += sstatus
     res += stvec
+    res += sie
     res += stimecmp
     res += sscratch
     res += sepc
+    res += sip
     res += sptbr
     res += sasid
-    res += scycle
+    res += cyclew
+    res += timew
+    res += instretw
     res += stime
-    res += sinstret
     res += scause
     res += sbadaddr
+    res += stimew
     res += mstatus
+    res += mtvec
+    res += mtdeleg
+    res += mie
+    res += mtimecmp
     res += mscratch
     res += mepc
     res += mcause
     res += mbadaddr
-    res += reset
-    res += tohost
-    res += fromhost
+    res += mip
+    res += mtime
+    res += mcpuid
+    res += mimpid
+    res += mhartid
+    res += mtohost
+    res += mfromhost
+    res += mreset
     res += send_ipi
-    res += hartid
     res.toArray
   }
   val all32 = {
@@ -314,9 +350,12 @@ object CSRs {
     res += cycleh
     res += timeh
     res += instreth
-    res += scycleh
+    res += cyclehw
+    res += timehw
+    res += instrethw
     res += stimeh
-    res += sinstreth
+    res += stimehw
+    res += mtimeh
     res.toArray
   }
 }