summaryrefslogtreecommitdiff
path: root/common/Memtype.v
diff options
context:
space:
mode:
authorGravatar xleroy <xleroy@fca1b0fc-160b-0410-b1d3-a4f43f01ea2e>2012-05-26 07:32:01 +0000
committerGravatar xleroy <xleroy@fca1b0fc-160b-0410-b1d3-a4f43f01ea2e>2012-05-26 07:32:01 +0000
commit132e36fa0be63eb5672eda9168403d3fb74af2fa (patch)
tree33955e0ccb4210271c82326b941523e6e4b2c289 /common/Memtype.v
parent9ea00d39bb32c1f188f1af2745c3368da6a349c1 (diff)
CSE: add recognition of some combined operators, conditions, and addressing modes (cf. CombineOp.v)
Memory model: cleaning up Memdata Inlining and new Constprop: updated for ARM. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@1902 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
Diffstat (limited to 'common/Memtype.v')
-rw-r--r--common/Memtype.v1
1 files changed, 0 insertions, 1 deletions
diff --git a/common/Memtype.v b/common/Memtype.v
index a13e861..b7d953f 100644
--- a/common/Memtype.v
+++ b/common/Memtype.v
@@ -418,7 +418,6 @@ Axiom load_store_similar:
Axiom load_store_same:
forall chunk m1 b ofs v m2, store chunk m1 b ofs v = Some m2 ->
- Val.has_type v (type_of_chunk chunk) ->
load chunk m2 b ofs = Some (Val.load_result chunk v).
Axiom load_store_other: