From 132e36fa0be63eb5672eda9168403d3fb74af2fa Mon Sep 17 00:00:00 2001 From: xleroy Date: Sat, 26 May 2012 07:32:01 +0000 Subject: CSE: add recognition of some combined operators, conditions, and addressing modes (cf. CombineOp.v) Memory model: cleaning up Memdata Inlining and new Constprop: updated for ARM. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@1902 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e --- common/Memtype.v | 1 - 1 file changed, 1 deletion(-) (limited to 'common/Memtype.v') diff --git a/common/Memtype.v b/common/Memtype.v index a13e861..b7d953f 100644 --- a/common/Memtype.v +++ b/common/Memtype.v @@ -418,7 +418,6 @@ Axiom load_store_similar: Axiom load_store_same: forall chunk m1 b ofs v m2, store chunk m1 b ofs v = Some m2 -> - Val.has_type v (type_of_chunk chunk) -> load chunk m2 b ofs = Some (Val.load_result chunk v). Axiom load_store_other: -- cgit v1.2.3