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| author |  Lioncash <mathew1800@gmail.com> | 2015-07-16 22:08:07 -0400 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-07-16 22:08:12 -0400 |
| commit | 23dbbb786aad2d7e1d8b190296288900dde55f2d (patch) | |
| tree | 408be8e40c7edacb9447d59c743e0ad99108d096 /src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |
| parent | 078bf29d1d0b15a4c60e8baaa02fae5d90633300 (diff) | |
arm_dyncom_interpreter: Simplify assignment in SMLAW
Also a side-benefit of not having implementation-defined behavior.
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_interpreter.cpp')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index b00eb49a..34cfb8cb 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -5695,7 +5695,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF); const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16); - RD = (result & (0xFFFFFFFFFFFFFFFFLL >> 15)) >> 16; + RD = BITS(result, 16, 47); if ((result >> 16) != (s32)RD) cpu->Cpsr |= (1 << 27); |